參數(shù)資料
型號(hào)： ISL5217
廠(chǎng)商： Intersil Corporation
英文描述： Quad Programmable Up Converter
中文描述： 四可編程轉(zhuǎn)換器
文件頁(yè)數(shù)： 4/43頁(yè)
文件大?。?/td> 766K
代理商： ISL5217
4
Pin Descriptions (all signals are active high unless otherwise stated)
NAME
TYPE
DESCRIPTION
POWER SUPPLY
VCCC
-
Positive Device Core Power Supply Voltage, 2.5V
±
0.125V.
Positive Device Input/Output Power Supply Voltage, 3.3V
±
0.165V.
VCCIO
-
GND
-
Ground, 0V
MICROPROCESSOR INTERFACE AND CONTROL
CLK
I
Input Clock. All processing in the ISL5217 occurs on the rising edge of CLK.
RESET
I
Reset. (Active Low). Asserting reset will clear all configuration registers to their default values, halting all processing.
P<15:0>
I/O
Data bus. Bit 15 is the MSB.
A<6:0>
I
Address bus. Bit 6 is the MSB.
Chip Select. (active low). Enables device to respond to
μ
P access.
NOTE: See Appendix A, Errata Sheet.
CS
I
RDMODE
I
Read Mode. Read mode selects the Read/Write mode for the Microprocessor Interface. When low the device is
configured for separate RD and WR strobe inputs. When high the device is configured for a common Read/Write
and Data Strobe inputs. Internally pulled down.
WR
I
Write Strobe, (active low). Dual function input. The input is configured for Write Strobe when RDMODE is low. When
RDMODE is high the input is configured for Data Strobe.
Write Strobe. The data on P<15:0> is written to the destination selected by A<6:0> on the rising edge of WR when
CS is asserted (low).
Data Strobe. The data on P<15:0> is written to the destination selected by A<6:0> on the rising edge of Data strobe
when RD is low and CS is asserted (low) or read from the address selected by A<6:0> placed on P<15:0> when
RD is high and CS is asserted (low).
RD
I
Read Strobe (Active Low). Dual function input. The input is configured for Read Strobe when RDMODE is low.
When RDMODE is high the input is configured for Read/Write Strobe.
Read Strobe. The data at the address selected by A(6:0) is placed on P<15:0> when RD is asserted (low) and
CS is asserted (low).
Read/Write Strobe. Determines the type of
μ
P access.
OFFBIN
I
Offset Binary. When set to 1, the output data bus format is offset binary. When set to 0 the output data bus format
is 2’s complement.
OUTEN<1:0>
I
Output Three-state Control. OUTEN<1:0> is decoded to provide three-state control of the output data buses. When
TRITST is asserted, the three-state control divides the 80-bit output into eight groups of 10-bits each. When TRITST
is deasserted, the three-state control operates on the 20-bit real and imaginary cascade out data buses.
TRITST
I
Tester Three-State Control. This signal determines how the OUTEN<1:0> is decoded to provide the necessary
three-state controls when in normal or tester applications. Set low for normal operation.
SERIAL DATA / SYNCHRONIZATION AND FIFO STATUS
SDA, SDB,
SDC, SDD
I
Serial Data A-D. (SDX) Serial Data Input for the I and Q vectors. The processing channel selected for this data will
shift the data in on the rising edge of its serial TX clock. The data vectors are shifted in with the MSB first.
SCLKA,
SCLKB,
SCLKC,
SCLKD
O
SERIAL CLK A-D. (SCLKX) Dual function output. The output is SERIAL CLK when symbol data is input through
the serial data port. When symbol data is input through the
μ
P port the output is SAMPLE CLK 0-3. The polarity of
SCLKX is programmable.
Serial Clock. Programmable rate clock signal provided to the data source to shift serial data out. Programmed rates
can be CLK/(1-32), or 32x sample clock. See control word 0x17, bit 15 for shut-off conditioning.
SAMPLE CLK. Signal provided to the data source to indicate when data is being transferred from the FIFO to the
shaping filter. The SAMPLE CLK output is generated by the sample rate NCO and has approximately 50% duty
cycle. The sample is taken on the high-to-low transition.
FSRA,
FSRB,
FSRC,
FSRD
O
FRAME STROBE A-D. (FSRX) Multiple Function Output. When control word 0x0c, bit 11 is set to zero, the output
is FRAME STROBE when symbol data is input through the serial data port. When symbol data is input through the
μ
P port the output is FIFO READY 0-3. When control word 0x0c, bit 11 is set to one, the setting of the
FSRMode<1:0> bits in indirect address 0x407 determine the output. The polarity of FSRX is programmable.
FRAME STROBE. Signal provided to the data source to initiate a serial word transfer. Alternatively selectable
through Serial Control 0x11, bit 14 to be Epoch frame strobe. Epoch is a pre-carry out of the fixed integer divider
instead of the serial frame strobe. The Epoch pre-carry out is six clocks ahead of the true carry out and can be used
to synchronize fixed integer dividers of other devices. See control word 0x17, bit 15 for shut-off conditioning.
FIFO READY. Indicates the I and Q FIFO pointer is less than the programmed FIFO depth.
UPDX or TXENX: When 0x0c, bit 11 is set to one, and FSRMode<1:0> is set to 10, the internal channel UPDX is
output. When 0x0c, bit 11 is set to one, and FSRMode<1:0> is set to 11, the internal channel TXENX is output. See
Table 43 for additional details.
ISL5217
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