參數(shù)資料
型號(hào)： ISL5216KIZ
廠商： INTERSIL CORP
元件分類： 無繩電話/電話
英文描述： Four-Channel Programmable Digital DownConverter
中文描述： TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA196
封裝： 12 X 12 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, BGA-196
文件頁(yè)數(shù)： 39/65頁(yè)
文件大?。?/td> 1076K
代理商： ISL5216KIZ
39
July 8, 2005
TABLE 20. AGC GAIN READ STROBE REGISTER (IWA = *00Fh)
P(15:0)
FUNCTION
15:0
for RD;
N/A for WR
Writing to this location will sample the AGC loop filter output (forward gain value) to stabilize it for reading. The value is read from
this location after waiting the four clocks required for synchronization.
TABLE 21. AGC LOOP ATTACK/DECAY GAIN VALUES REGISTER (IWA = *010h)
P(31:0)
FUNCTION
31:24
Loop gain 0, decay gain value (signal decay, increase gain) 31:28 = EEEE (exponent), 27:24 = MMMM (mantissa).
23:16
Loop gain 1, decay gain value 23:20 = EEEE (exponent), 19:16 = MMMM (mantissa).
15:8
Loop gain 0, attack gain value (signal arrival, decrease gain) 15:12 = EEEE (exponent), 11:8 = MMMM (mantissa).
7:0
Loop gain 1, attack gain value 7:4 = EEEE (exponent), 3:0 = MMMM (mantissa).
TABLE 22. AGC GAIN LIMITS REGISTER (IWA = *011h)
P(31:0)
FUNCTION
31:16
Upper gain limit. See AGC section.
15:0
Lower gain limit. See AGC section.
TABLE 23. AGC THRESHOLD REGISTER (IWA = *012h)
P(31:0)
FUNCTION
15:0
AGC threshold. Equals 1.64676 times the desired magnitude of the I1/Q1 output.
TABLE 24. AGC/DISCRIMINATOR CONTROL REGISTER (IWA = *013h)
P(15:0)
FUNCTION
15:11
Set to zero.
10
μ
P AGC loop gain select.
9
Enable filter compute engine control of AGC loop gain. When this bit is set, bit 28 in the filter compute engine destination field selects
which loop gain to use with that filter output’s gain error. Setting bit 10 overrides this bit and forces a loop gain 1.
10:9
FUNCTION
Loop Gain 1 (
μ
P controlled)
Loop gain 0 (
μ
P controlled)
00
10
01
Loop Gain controlled by filter compute engine
Loop 1 (
μ
P override of filter compute engine)
11
8
Mean/Median. This bit controls the settling mode of the AGC. Mean mode settles to the mean of the signal and settles asymptotically
to the final value. Median mode settles to the median and settles with a fixed step size. This mode settles faster and more predictably,
but will have more AM after settling.
1
Mean mode
0
Median mode
7
dphi / dt strobe enable. Set this bit to 1 to get a dphi/dt output without having to feed back through the filter compute engine.
6
Unused. Set to zero.
5
PhaseOutputSel
1
d
φ
/dt
0
Phase
4:3
DiscShift(1:0). Shifts the phase up 0-, 1-, 2-, or 3-bit positions, discarding the bits shifted off the top. This makes the phase modulo
360, 180, 90, or 45 degrees to remove PSK modulation. The resulting phase is 18 bits.
2:0
DiscDelay(2:0). Sets the delay, in sample times, for the d
φ
/dt calculation.
000
1
111
8
ISL5216
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