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參數(shù)資料
| 型號： | ISL5216KIZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | Four-Channel Programmable Digital DownConverter |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA196 |
| 封裝： | 12 X 12 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, BGA-196 |
| 文件頁數(shù)： | 20/65頁 |
| 文件大小： | 1076K |
| 代理商： | ISL5216KIZ |
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20
July 8, 2005
28:18
Destination
Destination Field Bit Mapping
28
27
26
25
24
23
22
21
20
19
18
AGCLFGN AGCLF
Path1
Path0
OS
FB
F4
F3
F2
F1
F0
AGCLFGN AGC loop gain select. Only applies to Path 1.
Loop gain 0 or 1 if AGCLF bit is set. Set to 0 (1 is a test mode for future chips).
AGCLF
AGC loop filter enable. Only applies to Path 1. The AGC loop is updated with the magnitude
of this sample (Path(1:0) = 01).
Path(1:0)
Back End Data Routing Path Selection. (see Back End Data Routing figure)
00
Route output back to filter compute engine input to another FIR in the filter chain.
01
Route output thru the FIFO and AGC to outputs I1 and Q1.
10
Route output to I2 and Q2, bypassing the FIFO and AGC. This path
also routes to next channel FIR input.
11
Route output thru the FIFO and AGC to outputs I2 and Q2.
OS
Enable output strobe. Setting this bit generates a data ready signal when the data reaches
the output section and starts the serial output sequence (paths 1, 2, 3). If OS is not set,
there will be no output to the outside world from this channel, for that output calculation, but
the data will be loaded into its output holding register (OS would not be set when routing the
data to another back end when cascading channels).
FB
Feedback data path. When set, the magnitude and dphi/dt from the cartesian-to-polar coor-
dinate converter block are routed to the filter compute engine input (magnitude goes to the
I input and dphi/dt goes to the Q input). Provided for discriminator filtering.
F(4:0)
Filter select. For data recirculated to the input of the FIR processor by path 0 or from the
cartesian to polar coordinate converter output, these bits tell which filter sequencer step
gets it as an input.
31:29
Round Select
31:29
Round Select (Add rounding bit at specified location).
000
2
-24
, use this code when downshifting is not used.
001
2
-23
010
2
-22
011
2
-21
100
2
-20
101
2
-19
110
2
-18
111
no rounding.
Provided for use with the coefficient down-shift bits.
41:32
Data Memory
Block Start
Memory block base address, 0-1023, 0-383 are valid for the ISL5216.
44:42
Data Memory
Block Size
44:42
Block Size.
0
8
1
16
2
32
3
64
4
128
5
256
6
512
7
(modulo addressing is used).
1024
52:45
Data Memory
Block-to-Block Step
0-255, usually equal to the decimation factor for the FIR in this instruction.
62:53
Coefficient Memory
Block Start
Memory base address of coefficients, 0-1023, 0-511 are valid on the ISL5216.
INSTRUCTION BIT FIELDS (Continued)
BIT
POSITIONS
FUNCTION
DESCRIPTION
ISL5216
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相關(guān)代理商/技術(shù)參數(shù) |
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| ISL5217 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Quad Programmable Up Converter |
| ISL5217_05 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Quad Programmable Up Converter |
| ISL5217EVAL1 | 功能描述:EVALUATION BOARD FOR ISL5217KI RoHS:是 類別:RF/IF 和 RFID >> RF 評估和開發(fā)套件，板 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:GPS 接收器 頻率:1575MHz 適用于相關(guān)產(chǎn)品:- 已供物品:模塊 其它名稱:SER3796 |
| ISL5217KI | 功能描述:上下轉(zhuǎn)換器 196BGA,-40+85C PROGRAMMABLE QUAD UP CONVERTER RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| ISL5217KIZ | 制造商:Intersil Corporation 功能描述:UP/DOWN CONV MIXER 2.5V 196BGA - Trays 制造商:Intersil 功能描述:W/ANNEAL 196BGA -40+ 85C PROG CONVER |
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