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參數(shù)資料
| 型號： | ISL51002EVALZ |
| 廠商： | Intersil Corporation |
| 英文描述： | 10-Bit Video Analog Front End (AFE) with Measurement and Auto-Adjust Features |
| 中文描述： | 10位的測量和自動(dòng)視頻模擬前端（AFE），調(diào)節(jié)功能 |
| 文件頁數(shù)： | 14/32頁 |
| 文件大?。?/td> | 360K |
| 代理商： | ISL51002EVALZ |
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14
December 22, 2006
0x19
Red Offset LSB,(0x00)
5:0
N/A
7:6
Red Offset LSB
2 LSBs of 10-bit offset word
0x1A
Green Offset MSB, (0x80)
7:0
Green Offset MSB
ABLC off: upper 8 bits to Green offset DAC
ABLC enabled: Green digital offset
(See Red Offset)
0x1B
Green Offset LSB, (0x00)
5:0
N/A
7:6
Green Offset LSB
See Red Offset
0x1C
Blue Offset MSB, (0x80)
7:0
Blue Offset MSB
ABLC off: upper 8 bits to Blue offset DAC
ABLC enabled: Blue digital offset
(See Red Offset)
0x1D
Blue Offset LSB, (0x00)
5:0
N/A
7:6
Blue Offset LSB
See Red Offset
0x1E
PLL Htotal MSB,(0x06)
5:0
PLL Htotal MSB
14-bit HTOTAL
PLL updated on LSB write only.
0x1F
PLL Htotal LSB,(0x98)
7:0
PLL Htotal LSB
PLL updated on LSB write only. SXGA default
0x20
PLL Phase,
(0x00)
5:0
PLL Sampling Phase
Used to control the phase of the ADC’s sample point relative
to the period of a pixel. Adjust to obtain optimum image quality.
One step = 5.625° (1.56% of pixel period).
0x21
PLL Pre-coast, (0x04)
7:0
Pre-coast
Number of lines the PLL will coast prior to the start of VSYNC.
0x22
PLL Post-coast, (0x04)
7:0
Post-coast
Number of lines the PLL will coast after the end of VSYNC.
0x23
PLL Misc, (0x00)
0
PLL Lock Edge HSYNC
0: PLL locks to trailing edge of selected HSYNC (default)
1: PLL locks to leading edge of selected HSYNC
1
CLKINV ENABLE
0: CLKINV input ignored
1: CLKINV input enabled
2
Ext Coast SEL
0: Internal COAST generation
1: External COAST source
3
Ext Coast POL
0: Active high external COAST
1: Active low external COAST
4
EXT CLOCK
0: Internal pixel clock from DPLL
1: External pixel clock from EXTCLKin pin
0x24
DC Restore and ABLC
starting pixel MSB, (0x00)
5:0
DC Restore and ABLC
starting pixel (MSB)
Pixel after Raw HSYNC trailing edge to begin DC restore and
ABLC. 14 bits.
0x25
DC Restore and ABLC
starting pixel LSB, (0x02)
7:0
DC Restore and ABLC
starting pixel (LSB)
0x26
DC Restore Clamp Width,
(0x10)
7:0
DC Restore clamp width
Only applies to DC restore clamp used for AC-coupled
configurations. A value of 0x00 means the clamp DAC is
never connected to the input.
Register Listing
(Continued)
ADDRESS
REGISTER
(DEFAULT VALUE)
BITS
FUNCTION NAME
DESCRIPTION
ISL51002
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISL51002 | 10-Bit Video Analog Front End (AFE) with Measurement and Auto-Adjust Features(具有測量和音頻調(diào)節(jié)功能的10-Bit視頻模擬前端(AFE)) |
| ISL5120IHZ-T | Low-Voltage, Single Supply, Dual SPST, SPDT Analog Switches |
| ISL5120IH-T | Low-Voltage, Single Supply, Dual SPST, SPDT Analog Switches |
| ISL5120IB | Low-Voltage, Single Supply, Dual SPST, SPDT Analog Switches |
| ISL5120IBZ | Low-Voltage, Single Supply, Dual SPST, SPDT Analog Switches |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISL51002-EVALZ | 功能描述:EVAL BOARD FOR ISL51002 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:* 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電源管理，電池充電器 嵌入式:否 已用 IC / 零件:MAX8903A 主要屬性:1 芯鋰離子電池 次要屬性:狀態(tài) LED 已供物品:板 |
| ISL5100A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Quad 18V Pin Electronics Driver/Window Comparator |
| ISL5101IB | 制造商:Intersil Corporation 功能描述: |
| ISL5120 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Low-Voltage, Single Supply, Dual SPST, SPDT Analog Switches |
| ISL5120CB | 功能描述:IC SWITCH DUAL SPST 8SOIC RoHS:否 類別:集成電路 (IC) >> 接口 - 模擬開關(guān)，多路復(fù)用器，多路分解器 系列:- 標(biāo)準(zhǔn)包裝:48 系列:- 功能:開關(guān) 電路:4 x SPST - NO 導(dǎo)通狀態(tài)電阻:100 歐姆 電壓電源:單/雙電源 電壓 - 電源，單路/雙路(±):2 V ~ 12 V，±2 V ~ 6 V 電流 - 電源:50nA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:管件 |
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