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參數(shù)資料
| 型號(hào)： | ISL45042 |
| 廠商： | Intersil Corporation |
| 英文描述： | LCD Module Calibrator |
| 中文描述： | 液晶顯示模塊校準(zhǔn) |
| 文件頁(yè)數(shù)： | 5/7頁(yè) |
| 文件大?。?/td> | 198K |
| 代理商： | ISL45042 |
5
FN6072.3
June 21, 2005
Adjustable Sink Current Output
The device provides an output sink current which lowers the
voltage on the external voltage divider. The equations that
control the output are given below. See Figure 1.
NOTE: Where setting is an integer between 1 and 128.
Replacing Existing Mechanical Potentiometer
Circuits
Figure 2 shows the common adjustment mechanical circuits
and equivalent replacement with the ISL45042.
7-Bit UP/DOWN Counter
The counter sets the level to the digital potentiometer and is
connected to the non-volatile memory. When the part is
programmed, the counter setting is loaded into the
non-volatile memory. This value will be loaded from the
non-volatile memory into the counter during power-on. The
counter will not exceed its maximum level and will hold that
value during subsequent increment requests on the CTL pin.
The counter will not exceed its minimum level and will hold
that value during subsequent decrement requests on the
CTL pin.
CTL Pin
CTL should have a noise filter to reduce bouncing or noise
on the input that could cause unwanted counting when the
CE pin is high. The board should have an additional ESD
protection circuit, with a series 1k
resistor and a shunt
0.01μF capacitor connected on the CTL pin. (See Figure 3)
In order to increment the setting, pulse CTL low for more
than 200μs. The output sink current increases and lowers
the VCOM lever by one least-significant bit (LSB). On the
other hand, to decrement the setting, pulse CTL high for
more than 200μs. The output sink current will decrease, and
the VCOM level will increase by one LSB.
To avoid unintentional adjustment, the ISL45042 guarantees
to reject CTL pulses shorter than 20μs.
To avoid the possibility of a false pulse (since the internal
comparators come up in an unknown state) the very first
CTL pulse is ignored. See Figure 4 for the timing
information.
.
NOTE: ‘CE’ should be disabled (pulled low) before powering the
device down to assure that the glitches and transients will not cause
unwanted EEPROM overwriting.
NOTE: In case where CE is tied to VDD, CTL pin should be tied to
ground (pulled low) when the programming is finished (should not
move the counter as the first pulse after programming is ignored),
and before the power-down. This will assure that no glitches or
transients on CTL input would cause unwanted counter movements.
IOUT
S128
)
20 RSET
=
VOUT
+
R1
R2
------R2
VAVDD 1
S128
)
20 RSET
–
=
-
+
R
a
R
b
R
c
R
SET
-
+
ISL45042
SET
OUT
AVDD
R
1
R
2
AVDD
VCOM
VCOM
AVDD
R
1
= Ra
R
2
= Rb + Rc
R
SET
= (Ra(Rb + Rc)) / 20Rb
FIGURE 2. EXAMPLE OF THE REPLACEMENT FOR THE MECHANICAL POTENTIOMETER CIRCUIT USING THE ISL45042
TABLE 1. TRUTH TABLE
INPUT
OUTPUT
CTL
CE
VDD
SET
ICC
MEMORY
Mid to Hi
Hi
VDD
Decrement
Normal
X
Mid to Lo
Hi
VDD
Increment
Normal
X
X
Lo
VDD
No Change
Lower
X
>4.9V
X
VDD
No Change
Increased
Program
X
X
0 to VDD
Read
Increased
Read
FIGURE 3. EXTERNAL ESD PROTECTION ON CTL PIN
ISL45042
CTL
0.01μF
1k
ISL45042
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