參數(shù)資料
型號(hào): ISL45042
廠商: Intersil Corporation
英文描述: LCD Module Calibrator
中文描述: 液晶顯示模塊校準(zhǔn)
文件頁(yè)數(shù): 2/7頁(yè)
文件大小: 198K
代理商: ISL45042
2
FN6072.3
June 21, 2005
Pin Descriptions
PIN
FUNCTION
OUT
Adjustable Sink Current Output Pin. The current sinks into the OUT pin is equal to the DAC setting times the maximum adjustable sink
current divided by 128. See SET pin function description for the maxim adjustable sink current setting.
AVDD
High-Voltage Analog Supply. Bypass to GND with 0.1μF capacitor.
N/C
No Connect. Not internally connected.
GND
Ground connection.
V
DD
System power supply input. Bypass to GND with 0.1μF capacitor.
CTL
Internal Counter Up/Down Control and Internal EEPROM Programming Control Input. If CE is high, a mid-to-low transition increments
the 7-bit counter, raising the DAC setting, increasing the OUT sink current, and lowering the divider voltage at OUT. A mid-to-high
transition decrements the 7-bit counter, lowering the DAC setting, decreasing the OUT sink current, and increasing the divider voltage
at OUT. Applying 4.9V and above with appropriately arranged timing will overwrite EEPROM with the contents in the 7-bit counter.
See EEPROM Programming section for details.
CE
Counter Enable Pin. Connect CE to V
DD
to enable counting of the internal counter. Connect CE to GND to inhibit counting.
SET
Maximum Sink Current Adjustment Point. Connect a resistor from SET to GND to set the maximum adjustable sink current of the
OUT pin. The maximum adjustable sink current is equal to (AVDD/20) divided by RSET.
Block Diagram
ISL45042
DIGITAL INTERFACE
WITH THRESHOLD
SENSORS
UP/DOWN COUNTER
WITH PRESET
LATCHES
EEPROM
OR
NVL MEMORY
ANALOG DCP AND
CURRENT OUTPUT
BLOCK
AVDD
IOUT
SET
CTL
CE
V
DD
GND
UP
DWN
PWRUP
PRGM
POR
POR
PRGM
IBIAS
READ
PRGM MEMORY
ISL45042
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