參數(shù)資料
型號: ISL43L220
廠商: Intersil Corporation
英文描述: Ultra Low ON-Resistance, Low Voltage, Single Supply, Dual SPDT Analog Switch(超低導(dǎo)通電阻, 低電壓,單電源, 雙路單刀雙擲模擬開關(guān))
中文描述: 超低導(dǎo)通電阻,低電壓,單電源,雙路SPDT模擬開關(guān)(超低導(dǎo)通電阻,低電壓,單電源,雙路單刀雙擲模擬開關(guān))
文件頁數(shù): 13/13頁
文件大?。?/td> 437K
代理商: ISL43L220
13
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6093.2
April 12, 2005
ISL43L220
Thin Dual Flat No-Lead Plastic Package (TDFN)
//
NX (b)
SECTION "C-C"
FOR ODD TERMINAL/SIDE
e
C C
5
C
TERMINAL TIP
(A1)
BOTTOM VIEW
A
6
AREA
INDEX
C
C
0.10
0.08
SIDE VIEW
0.15
2X
E
A
B
C
0.15
D
TOP VIEW
C B
2X
6
8
AREA
INDEX
NX L
E2
E2/2
REF.
e
(Nd-1)Xe
N
(DATUM A)
(DATUM B)
5
0.10
8
7
D2
B
A
C
N-1
1
2
PLANE
SEATING
C
A
A3
NX b
D2/2
NX k
L1
9L
M
L10.3x3A
10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
SYMBOL
MILLIMETERS
NOTES
MIN
NOMINAL
MAX
A
0.70
0.75
0.80
-
A1
-
-
0.05
-
A3
0.20 REF
-
b
0.20
0.25
0.30
5,8
D
3.00 BSC
-
D2
2.20
2.30
2.40
7,8
E
3.00 BSC
-
E2
1.40
1.50
1.60
7,8
e
0.50 BSC
-
k
0.25
-
-
-
L
0.20
0.30
0.40
8
L1
-
-
0.15
1
N
10
2
Nd
5
3
Rev. 1 6/04
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd refers to the number of terminals on D.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
9. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
10. COMPLIANT TO JEDEC MO-229-WEED-3 except for
dimensions E2 & D2.
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ISL43L410 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Ultra Low ON-Resistance, Low Voltage, Single Supply, DPDT Analog Switch