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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | ISL28108FBZ-T7 |
| 寤犲晢锛� | Intersil |
| 鏂囦欢闋佹暩(sh霉)锛� | 15/34闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC OPAMP GP RR 1.2MHZ 8SOIC |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1,000 |
| 鏀惧ぇ鍣ㄩ鍨嬶細 | 閫氱敤 |
| 闆昏矾鏁�(sh霉)锛� | 1 |
| 杓稿嚭椤炲瀷锛� | 婊挎摵骞� |
| 杞�(zhu菐n)鎻涢€熺巼锛� | 0.45 V/µs |
| 澧炵泭甯跺绌嶏細 | 1.2MHz |
| 闆绘祦 - 杓稿叆鍋忓锛� | 13nA |
| 闆诲 - 杓稿叆鍋忕Щ锛� | 25µV |
| 闆绘祦 - 闆绘簮锛� | 185µA |
| 闆绘祦 - 杓稿嚭 / 閫氶亾锛� | 30mA |
| 闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±)锛� | 3 V ~ 40 V锛�±1.5 V ~ 20 V |
| 宸ヤ綔婧害锛� | -40°C ~ 125°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 8-SOIC锛�0.154"锛�3.90mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 8-SOIC |
| 鍖呰锛� | 甯跺嵎 (TR) |
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ISL28108, ISL28208, ISL28408
FN6935.5
March 4, 2014
Unused Channels
If the application requires only one channel, the user must
configure any unused channel to prevent it from oscillating.
Unused channels can oscillate if the input and output pins are
floating. This will result in higher-than-expected supply currents
and possible noise injection into the channel being used. The
proper way to prevent oscillation is to short the output to the
inverting input, and ground the positive input (Figure 66).
Power Dissipation
It is possible to exceed the +150掳C maximum junction
temperatures under certain load and power supply conditions. It
is therefore important to calculate the maximum junction
temperature (TJMAX) for all applications to determine if power
supply voltages, load conditions, or package type need to be
modified to remain in the safe operating area. These parameters
are related using Equation 1:
where:
PDMAXTOTAL is the sum of the maximum power dissipation of
each amplifier in the package (PDMAX)
where:
TMAX = Maximum ambient temperature
胃JA = Thermal resistance of the package
PDMAX = Maximum power dissipation of 1 amplifier
VS = Total supply voltage
IqMAX = Maximum quiescent supply current of 1 amplifier
VOUTMAX = Maximum output voltage swing of the application
RL = Load resistance
ISL28108, ISL28208, ISL28408 SPICE Model
the net list for the SPICE model. The model is a simplified version
of the actual device and simulates important AC and DC
parameters. AC parameters incorporated into the model are: 1/f
and flat band noise voltage, Slew Rate, CMRR, Gain and Phase.
The DC parameters are IOS, total supply current and output voltage
swing. The model uses typical parameters given in the 鈥淓lectrical
Specifications鈥� Table beginning on page 6. The AVOL is adjusted
for 122dB with the dominant pole at 1Hz. The CMRR is set 128dB,
f = 6kHz. The input stage models the actual device to present an
accurate AC representation. The model is configured for ambient
temperature of +25掳C.
results for the Noise Voltage, Open Loop Gain Phase, Closed Loop
Gain vs Frequency, Gain vs Frequency vs RL, CMRR, Large Signal
10V Step Response, Small Signal 0.05V Step and Output Voltage
Swing 卤15V supplies.
LICENSE STATEMENT
The information in this SPICE model is protected under the
United States copyright laws. Intersil Corporation hereby grants
users of this macro-model hereto referred to as 鈥淟icensee鈥�, a
nonexclusive, nontransferable licence to use this model as long
as the Licensee abides by the terms of this agreement. Before
using this macro-model, the Licensee should read this license. If
the Licensee does not accept these terms, permission to use the
model is not granted.
The Licensee may not sell, loan, rent, or license the
macro-model, in whole, in part, or in modified form, to anyone
outside the Licensee鈥檚 company. The Licensee may modify the
macro-model to suit his/her specific applications, and the
Licensee may make copies of this macro-model for use within
their company only.
This macro-model is provided 鈥淎S IS, WHERE IS, AND WITH NO
WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED,
INCLUDING, BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.鈥�
In no event will Intersil be liable for special, collateral, incidental,
or consequential damages in connection with or arising out of
the use of this macro-model. Intersil reserves the right to make
changes to the product and the macro-model without prior
notice.
FIGURE 66. PREVENTING OSCILLATIONS IN UNUSED CHANNELS
-
+
T
JMAX
T
MAX
胃
JAxP DMAXTOTAL
+
=
(EQ. 1)
PD
MAX
V
S
I
qMAX
V
S
(
- V
OUTMAX )
V
OUTMAX
R
L
----------------------------
脳
+
脳
=
(EQ. 2)
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| TLC2272CPSG4 | IC OPAMP GP R-R 2.25MHZ 8SOIC |
| 961238-6700-AR-PT | CONN HEADER STR DL 38PS GOLD SMD |
| 53610-S20-4 | EJC LTC.100"SHD HD.0100"VER 15GD |
| 108457096002049 | CONN HEADER MALE 96POS R/A |
| 1.5KE68ARL4G | TVS 1500W 68V UNIDIRECT AXIAL |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| ISL28108FBZ-T7A | 鍔熻兘鎻忚堪:閬�(y霉n)绠楁斁澶у櫒 - 閬�(y霉n)鏀� ISL28108FBZ 40V LW PWR RAIL-RAIL OUT RoHS:鍚� 鍒堕€犲晢:STMicroelectronics 閫氶亾鏁�(sh霉)閲�:4 鍏辨ā鎶戝埗姣旓紙鏈€灏忓€硷級:63 dB 杓稿叆瑁�(b菙)鍎熼浕澹�:1 mV 杓稿叆鍋忔祦锛堟渶澶у€硷級:10 pA 宸ヤ綔闆绘簮闆诲:2.7 V to 5.5 V 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:QFN-16 杞�(zhu菐n)鎻涢€熷害:0.89 V/us 闂�(gu膩n)闁�:No 杓稿嚭闆绘祦:55 mA 鏈€澶у伐浣滄韩搴�:+ 125 C 灏佽:Reel |
| ISL28108FRTZ | 鍔熻兘鎻忚堪:鏀惧ぇ鍣� IC 闁嬬櫦(f膩)宸ュ叿 ISL28108FRTZ 40V LW PWR R-R OUT SNGL SUP RoHS:鍚� 鍒堕€犲晢:International Rectifier 鐢�(ch菐n)鍝�:Demonstration Boards 椤炲瀷:Power Amplifiers 宸ュ叿鐢ㄤ簬瑭曚及:IR4302 宸ヤ綔闆绘簮闆诲:13 V to 23 V |
| ISL28108FRTZ-T13 | 鍔熻兘鎻忚堪:鏀惧ぇ鍣� IC 闁嬬櫦(f膩)宸ュ叿 ISL28108FRTZ 40V LW PWR R-R OUT SNGL SUP RoHS:鍚� 鍒堕€犲晢:International Rectifier 鐢�(ch菐n)鍝�:Demonstration Boards 椤炲瀷:Power Amplifiers 宸ュ叿鐢ㄤ簬瑭曚及:IR4302 宸ヤ綔闆绘簮闆诲:13 V to 23 V |
| ISL28108FRTZ-T7 | 鍔熻兘鎻忚堪:鏀惧ぇ鍣� IC 闁嬬櫦(f膩)宸ュ叿 ISL28108FRTZ 40V LW PWR R-R OUT SNGL SUP RoHS:鍚� 鍒堕€犲晢:International Rectifier 鐢�(ch菐n)鍝�:Demonstration Boards 椤炲瀷:Power Amplifiers 宸ュ叿鐢ㄤ簬瑭曚及:IR4302 宸ヤ綔闆绘簮闆诲:13 V to 23 V |
| ISL28108FRTZ-T7A | 鍔熻兘鎻忚堪:閬�(y霉n)绠楁斁澶у櫒 - 閬�(y霉n)鏀� ISL28108FRTZ 40V LW RAIL OUT SNG SUPP RoHS:鍚� 鍒堕€犲晢:STMicroelectronics 閫氶亾鏁�(sh霉)閲�:4 鍏辨ā鎶戝埗姣旓紙鏈€灏忓€硷級:63 dB 杓稿叆瑁�(b菙)鍎熼浕澹�:1 mV 杓稿叆鍋忔祦锛堟渶澶у€硷級:10 pA 宸ヤ綔闆绘簮闆诲:2.7 V to 5.5 V 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:QFN-16 杞�(zhu菐n)鎻涢€熷害:0.89 V/us 闂�(gu膩n)闁�:No 杓稿嚭闆绘祦:55 mA 鏈€澶у伐浣滄韩搴�:+ 125 C 灏佽:Reel |
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