21 FN6935.5 March 4, 2014 Submit Document Feedback Applications Information Functional Description The ISL2" />
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鍨嬭櫉(h脿o)锛� ISL28108FBZ-T7
寤犲晢锛� Intersil
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 14/34闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC OPAMP GP RR 1.2MHZ 8SOIC
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 1,000
鏀惧ぇ鍣ㄩ鍨嬶細 閫氱敤
闆昏矾鏁�(sh霉)锛� 1
杓稿嚭椤炲瀷锛� 婊挎摵骞�
杞�(zhu菐n)鎻涢€熺巼锛� 0.45 V/µs
澧炵泭甯跺绌嶏細 1.2MHz
闆绘祦 - 杓稿叆鍋忓锛� 13nA
闆诲 - 杓稿叆鍋忕Щ锛� 25µV
闆绘祦 - 闆绘簮锛� 185µA
闆绘祦 - 杓稿嚭 / 閫氶亾锛� 30mA
闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±)锛� 3 V ~ 40 V锛�±1.5 V ~ 20 V
宸ヤ綔婧害锛� -40°C ~ 125°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 8-SOIC锛�0.154"锛�3.90mm 瀵級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 8-SOIC
鍖呰锛� 甯跺嵎 (TR)
ISL28108, ISL28208, ISL28408
FN6935.5
March 4, 2014
Applications Information
Functional Description
The ISL28108, ISL28208, and ISL28408 are single, dual and
quad, 1.2MHz, single supply rail-to-rail output amplifiers with a
common mode input voltage range extending to a range of 0.5V
below the V- rail. Their input stages are optimized for precision
sensing of ground referenced signals in low voltage, single supply
applications. The input stage has the capability of handling large
input differential voltages without phase inversion making them
suitable for high voltage comparator applications. Their bipolar
design features high open loop gain and excellent DC input and
output temperature stability. These op amps feature low quiescent
current of 165A, and a maximum temperature drift ranging from
1.1V/掳C for the ISL28208 and ISL28408 in the SOIC package to
1.4V/掳C for the ISL28208 in the TDFN package and the ISL28408
in the SOIC package (see Figures 11 through 20). All devices are
fabricated in a new precision 40V complementary bipolar DI process
and immune from latch-up.
Operating Voltage Range
The devices are designed to operate over the 3V (卤1.5V) to
40V (卤20V) range and are fully characterized at 卤5V and 卤15V. Both
DC and AC performance remain virtually unchanged over the 卤5V
to 卤15V operating voltage range. Parameter variation with
operating voltage is shown in the 鈥淭ypical Performance Curves鈥�
beginning on page 10.
Input Stage Performance
The PNP input stage has a common mode input range extending
up to 0.5V below ground at +25掳C (see Figures 23 and 24). Full
amplifier performance is guaranteed down to ground (V-) over the
-40掳C to +125掳C temperature range. For common mode voltages
down to -0.5V the amplifiers are fully functional, but performance
degrades slightly over the full temperature range. This feature
provides excellent CMRR, AC performance and DC accuracy when
amplifying low level ground referenced signals.
The input stage has a maximum input differential voltage equal
to a diode drop greater than the supply voltage (max 42V) and
does not contain the back-to-back input protection diodes found
on many similar amplifiers. This feature enables the device to
function as a precision comparator by maintaining very high
input impedance for high voltage differential input comparator
voltages. The high differential input impedance also enables the
device to operate reliably in large signal pulse applications
without the need for anti-parallel clamp diodes required on
MOSFET and most bipolar input stage op amps. Thus, input
signal distortion caused by nonlinear clamps under high slew
rate conditions are avoided.
In applications where one or both amplifier input terminals are at
risk of exposure to voltages beyond the supply rails, current
limiting resistors may be needed at each input terminal
(see Figure 65, RIN+, RIN-) to limit current through the power
supply ESD diodes to 20mA.
Output Drive Capability
The bipolar rail-to-rail output stage features low saturation levels
that enable an output voltage swing to less than 10mV when the
total output load (including feedback resistance) is held below
50A (Figures 31 and 32). With 卤15V supplies this can be
achieved by using feedback resistor values >300k. The low input
bias and offset currents (-43nA and 卤3nA +25掳C max
respectively) minimize DC offset errors at these high resistance
values. For example, a balanced 4 resistor gain circuit (Figure 65)
with 1M feedback resistors (RF, RG) generates a worst case
input offset error of only 卤3mV. Furthermore, the low noise
current reduces the added noise associated with high feedback
resistance.
The output stage is internally current limited. Output current limit
over-temperature is shown in Figures 37 and 38. The amplifiers
can withstand a short circuit to either rail as long as the power
dissipation limits are not exceeded. This applies to only one
amplifier at a time for the dual op amp. Continuous operation
under these conditions may degrade long-term reliability.
The amplifiers perform well driving capacitive loads
(Figures 60 and 61). The unity gain, voltage follower (buffer)
configuration provides the highest bandwidth, but is also the
most sensitive to ringing produced by load capacitance found in
BNC cables. Unity gain overshoot is limited to 30% at
capacitance values to 0.33nF. At gains of 10 and higher, the
device is capable of driving more than 10nF without significant
overshoot.
Output Phase Reversal
Output phase reversal is a change of polarity in the amplifier
transfer function when the input voltage exceeds the supply
voltage. These devices are immune to output phase reversal, out
to 0.5V beyond the rail (VABS MAX) limit (see Figure 40).
FIGURE 65. INPUT ESD DIODE CURRENT LIMITING
-
+
RIN-
RL
VIN-
V+
V-
RIN+
VIN+
RF
RG
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
TLC2272CPSG4 IC OPAMP GP R-R 2.25MHZ 8SOIC
961238-6700-AR-PT CONN HEADER STR DL 38PS GOLD SMD
53610-S20-4 EJC LTC.100"SHD HD.0100"VER 15GD
108457096002049 CONN HEADER MALE 96POS R/A
1.5KE68ARL4G TVS 1500W 68V UNIDIRECT AXIAL
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