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參數(shù)資料
| 型號： | ISL267817IUZ-T7A |
| 廠商： | Intersil |
| 文件頁數(shù)： | 6/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT SPI/SRL 200K 8MSOP |
| 標準包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 2.15mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 8-MSOP |
| 包裝： | 標準包裝 |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
| 其它名稱： | ISL267817IUZ-T7ADKR |
ISL267817
14
FN7877.2
April 19, 2012
sample rate then the average power consumption of the ADC is
roughly constant, decreasing somewhat at lower throughput
rates (Figure 35).
The shutdown current is impacted by the state of the CS/SHDN
pin, as shown in Figure 36.
Serial Digital Interface
Conversion data is accessed with an SPI-compatible serial
interface. The interface consists of the data clock (DCLOCK),
serial data output (DOUT), and chip select/shutdown (CS/SHDN).
A falling edge on the CS/SHDN signal initiates a conversion by
placing the part into the acquisition (ACQ) phase. After tACQ has
elapsed, the part enters the conversion (CONV) phase and begins
outputting the conversion result starting with a null bit followed
by the most significant bit (MSB) and ending with the least
significant bit (LSB). The CS/SHDN pin can be pulled high at this
point to put the device into Standby mode and reduce the power
consumption. If CS/SHDN is held low after the LSB bit has been
output, the conversion result will be repeated in reverse order
until the MSB is transmitted, after which the serial output enters
a high impedance state. The ISL267817 will remain in this state,
dissipating typical dynamic power levels, until CS/SHDN
transitions high then low to initiate the next conversion.
Data Format
Output data is encoded in two’s complement format, as shown in
Table 1. The voltage levels in the table are idealized and don’t
account for any gain/offset errors or noise.
TERMINOLOGY
Signal-to-(Noise + Distortion) Ratio (SINAD)
This is the measured ratio of signal-to-(noise + distortion) at the
output of the ADC. The signal is the RMS amplitude of the
fundamental. Noise is the sum of all non-fundamental signals up
to half the sampling frequency (fs/2), excluding DC. The ratio
is dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the quantization
noise. The theoretical signal-to-(noise + distortion) ratio for an
ideal N-bit converter with a sine wave input is given by
Equation 1:
Thus, for a 12-bit converter this is 74dB, and for a 10-bit this is
62dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS sum of
harmonics to the fundamental. For the ISL267817, it is defined
as Equation 2:
FIGURE 34. POWER CONSUMPTION vs SAMPLE RATE, fCLK = 3.2MHz
FIGURE 35. SHUTDOWN CURRENT vs SAMPLE RATE,
fCLK = 16 fSAMPLE
FIGURE 36. SHUTDOWN CURRENT vs SAMPLE RATE
1
10
100
1000
1
10
100
1k
SAMPLE RATE (kHz)
TA= +25°C
VCC = 5V
VREF = 2.5V
fCLK = 3.2MHz
SUPPLY
CURRENT
1
10
100
1000
1
10
100
1k
SAMPLE RATE (kHz)
TA= +25°C
VCC = 5V
VREF = 2.5V
fCLK= 16 fSAMPLE
SUPP
LY
CURRENT
(A)
0
10
20
30
40
50
60
110
100
1k
SAMPLE RATE (kHz)
SUP
P
LY
CU
RRE
N
T
(A)
CSB = HIGH
(VCC)
CSB = LOW
(GND)
TABLE 1. TWO’S COMPLEMENT DATA FORMATTING
INPUT
VOLTAGE
DIGITAL OUTPUT
–Full Scale
–VREF
1000 0000 0000
–Full Scale + 1LSB
–VREF+ LSB
1000 0000 0001
Midscale
0
0000 0000 0000
+Full Scale – 1LSB
+VREF– 1 LSB
0111 1111 1110
+Full Scale
+VREF – LSB
0111 1111 1111
Signal-to-(Noise + Distortion)
6.02 N
1.76
+
()dB
=
(EQ. 1)
(EQ. 2)
THD dB
()
20
V
2
V
3
2
V
4
2
V
5
2
V
6
2
++
V
1
2
------------------------------------------------------------------------
log
=
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