13 FN8273.1 September 5, 2013 Analog Inputs Some members of the ISL26320, " />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� ISL26323FBZ-T
寤犲晢锛� Intersil
鏂囦欢闋佹暩(sh霉)锛� 5/23闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC ADC 12BIT SPI/SRL 250K 8SOIC
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 2,500
浣嶆暩(sh霉)锛� 12
閲囨ǎ鐜囷紙姣忕锛夛細 250k
鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� 涓茶锛孲PI?
杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 1
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闆诲闆绘簮锛� 鍠浕婧�
宸ヤ綔婧害锛� -40°C ~ 125°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 8-SOIC锛�0.154"锛�3.90mm 瀵級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 8-SOIC
鍖呰锛� 甯跺嵎 (TR)
杓稿叆鏁�(sh霉)鐩拰椤炲瀷锛� 2 鍊嬪柈绔�锛屽柈妤�
ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329
13
FN8273.1
September 5, 2013
Analog Inputs
Some members of the ISL26320, ISL26321, ISL26322,
ISL26323, ISL26324, ISL26325 and ISL26329 family feature a
fully differential input with a nominal full-scale range equal to
twice the applied VREF voltage. Those devices with differential
inputs have a nominal full scale range equal to twice the applied
VREF voltage. Each input swings VREF volts (peak-to-peak), 180掳
out of phase from one another for a total differential input of
2*VREF (refer to Figures 23 and 24).
Differential signaling offers several benefits over a single-ended
input, such as:
Doubling of the full-scale input range (and therefore the
dynamic range)
Improved even order harmonic distortion
Better noise immunity due to common mode rejection
Figure 24 shows the relationship between the reference voltage
and the full-scale differential input range for two different values
of VREF. Note that the common-mode input voltage must be
maintained within 卤200mV of VREF/2 for differential inputs.
Those devices with singled-ended inputs have a ground-referenced
peak-to-peak input voltage span equal to the reference voltage.
FIGURE 21. IDEAL TRANSFER CHARACTERISTICS, DIFFERENTIAL INPUT
FIGURE 22. IDEAL TRANSFER CHARACTERISTICS, SINGLE-ENDED INPUT
1LSB = 2VREF/4096
100...000
100...001
100...010
111...111
000...000
000...001
011...110
011...111
AD
C
O
DE
ANALOG INPUT
AIN+ 鈥� (AIN鈥�)
鈥揤
REF
+ LSB
+VREF
鈥� 1LSB
0V
+VREF
鈥� 1LSB
1LSB = VREF/4096
000...000
000...001
000...010
011...111
100...000
100...001
111...110
111...111
AD
C
O
DE
ANALOG INPUT
0 = + LSB
FS = +VREF-1LSB
FIGURE 23. DIFFERENTIAL INPUT SIGNALING
ISL2631X/32X
VCM
VREF (P-P)
AIN+
AIN-
FIGURE 24. RELATIONSHIP BETWEEN VREF AND FULL-SCALE
RANGE FOR DIFFERENTIAL INPUTS
3.0
5.0
2.0
1.0
4.0
AIN+
AIN鈥�
2.5Vp-p
VREF = 2.5V
3.0
5.0
2.0
1.0
4.0
AIN+
AIN鈥�
VCM
5Vp-p
VREF = 5V
t
V
t
V
ALLOWABLE VCM RANGE
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
IDT7207L15JG IC FIFO 16384X18 15NS 32PLCC
IDT7207L15J IC FIFO 16384X18 15NS 32PLCC
MS27497T12A98PA CONN RCPT 10POS WALL MNT W/PINS
MS27466T15A15S CONN RCPT 15POS WALL MT W/SCKT
MS27499E10F35SA CONN RCPT 13POS BOX MNT W/SCKT
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鍙冩暩(sh霉)鎻忚堪
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ISL26324FVZ 鍔熻兘鎻忚堪:IC ADC 12BIT SPI/SRL 16-TSSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:250 绯诲垪:- 浣嶆暩(sh霉):12 閲囨ǎ鐜囷紙姣忕锛�:1.8M 鏁�(sh霉)鎿�(j霉)鎺ュ彛:骞惰伅(li谩n) 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:1 鍔熺巼鑰楁暎锛堟渶澶э級:1.82W 闆诲闆绘簮:妯℃摤鍜屾暩(sh霉)瀛� 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:48-LQFP 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:48-LQFP锛�7x7锛� 鍖呰:绠′欢 杓稿叆鏁�(sh霉)鐩拰椤炲瀷:2 鍊嬪柈绔紝鍠サ
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ISL26324FVZ-T7A 鍔熻兘鎻忚堪:IC ADC 12BIT SPI/SRL 4CH 16TSSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:1 绯诲垪:- 浣嶆暩(sh霉):10 閲囨ǎ鐜囷紙姣忕锛�:357k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:DSP锛孧ICROWIRE?锛孮SPI?锛屼覆琛�锛孲PI? 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:1 鍔熺巼鑰楁暎锛堟渶澶э級:830µW 闆诲闆绘簮:鍠浕婧� 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:10-WFDFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:10-TDFN-EP锛�3x3锛� 鍖呰:鍓垏甯� (CT) 杓稿叆鏁�(sh霉)鐩拰椤炲瀷:2 鍊嬪柈绔�锛屽柈妤�锛�2 鍊嬪柈绔紝闆欐サ锛�1 鍊嬪樊鍒�锛屽柈妤碉紱1 鍊嬪樊鍒�锛岄洐妤� 鐢�(ch菐n)鍝佺洰閷勯爜闈�:1396 (CN2011-ZH PDF) 鍏跺畠鍚嶇ū:MAX1395ETB+TCT
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*鍨嬭櫉 *鏁�(sh霉)閲� 寤犲晢 鎵硅櫉 灏佽
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