VCCRamp VCC " />
參數(shù)資料
型號： ISL22346WFV20Z-TK
廠商： Intersil
文件頁數(shù)： 13/16頁
文件大?。?/td> 0K
描述： IC POT DGTL 128TP LN LP 20-TSSOP
標準包裝： 1,000
系列： XDCP™
接片： 128
電阻（歐姆）： 10k
電路數(shù)： 4
溫度系數(shù)： 標準值 ±50 ppm/°C
存儲器類型： 非易失
接口： I²C（設備位址）
電源電壓： 2.7 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應商設備封裝： 20-TSSOP
包裝： 帶卷 (TR)
6
FN6177.2
September 3, 2009
VCCRamp VCC Ramp Rate
0.2
V/ms
tD
Power-up Delay
VCC above Vpor, to DCP Initial Value
Register recall completed, and I2C Interface
in standby state
3ms
EEPROM SPECIFICATION
EEPROM Endurance
1,000,000
Cycles
EEPROM Retention
Temperature T < +55°C
50
Years
tWC
(Note 19)
Non-volatile Write Cycle Time
12
20
ms
SERIAL INTERFACE SPECIFICATIONS
VIL
A2, A1, A0, SHDN, SDA, and SCL
Input Buffer LOW Voltage
-0.3
0.3*VCC
V
VIH
A2, A1, A0, SHDN, SDA, and SCL
Input Buffer HIGH Voltage
0.7*VCC
VCC + 0.3
V
Hysteresis
SDA and SCL Input Buffer Hysteresis
0.05*VCC
V
VOL
SDA Output Buffer LOW Voltage,
Sinking 4mA
00.4
V
Cpin
(Note 20)
A2, A1, A0, SHDN, SDA, and SCL Pin
Capacitance
10
pF
fSCL
SCL Frequency
400
kHz
tsp
Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the max spec is
suppressed
50
ns
tAA
SCL Falling Edge to SDA Output Data
Valid
SCL falling edge crossing 30% of VCC, until
SDA exits the 30% to 70% of VCC window
900
ns
tBUF
Time the Bus Must be Free Before the
Start of a New Transmission
SDA crossing 70% of VCC during a STOP
condition, to SDA crossing 70% of VCC
during the following START condition
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VCC crossing
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VCC crossing
600
ns
tSU:STA
START Condition Setup Time
SCL rising edge to SDA falling edge; both
crossing 70% of VCC
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing 30% of VCC
to SCL falling edge crossing 70% of VCC
600
ns
tSU:DAT
Input Data Setup Time
From SDA exiting the 30% to 70% of VCC
window, to SCL rising edge crossing 30% of
VCC
100
ns
tHD:DAT
Input Data Hold Time
From SCL rising edge crossing 70% of VCC
to SDA entering the 30% to 70% of VCC
window
0ns
tSU:STO
STOP Condition Setup Time
From SCL rising edge crossing 70% of VCC,
to SDA rising edge crossing 30% of VCC
600
ns
tHD:STO
STOP Condition Hold Time for Read,
or Volatile Only Write
From SDA rising edge to SCL falling edge;
both crossing 70% of VCC
1300
ns
tDH
Output Data Hold Time
From SCL falling edge crossing 30% of VCC,
until SDA enters the 30% to 70% of VCC
window
0ns
tR
SDA and SCL Rise Time
From 30% to 70% of VCC
20 +
0.1*Cb
250
ns
Operating Specifications Over the recommended operating conditions, unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 21)
TYP
(Note 5)
MAX
(Note 21)
UNIT
ISL22346
相關(guān)PDF資料
PDF描述
M83723/84W1831N CONN RCPT 31POS JAM NUT W/SCKT
DS1007S-2/T&R IC DELAY LINE 4NS 16-SOIC
DS1007S-12/T&R IC DELAY LINE 3NS 16-SOIC
VI-B5B-MY-F1 CONVERTER MOD DC/DC 95V 50W
ISL22346UFRT20Z-TK IC POT DGTL 128TP LN LP 20-TQFN
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISL22346WMVEP 制造商:Intersil Corporation 功能描述:DGTL POTENTIOMETER 128POS 10KOHM QUAD 20TSSOP - Rail/Tube
ISL22346WMVEP-TK 制造商:Intersil Corporation 功能描述:DGTL POTENTIOMETER 128POS 10KOHM QUAD 20TSSOP - Tape and Reel
ISL22349 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Quad Digitally Controlled Potentiometers
ISL22349_09 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Quad Digitally Controlled Potentiometers
ISL22349UFV14Z 功能描述:IC POT DGTL 128TP LN LP 14-TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 接片:32 電阻（歐姆）:50k 電路數(shù):1 溫度系數(shù):標準值 50 ppm/°C 存儲器類型:易失 接口:3 線串行（芯片選擇，遞增，增/減） 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 細型，TSOT-23-6 供應商設備封裝:TSOT-23-6 包裝:帶卷 (TR)
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*