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參數(shù)資料
| 型號(hào)： | ISL1220 |
| 廠商： | Intersil Corporation |
| 英文描述： | Low Power RTC with 8 Bytes of Battery Backed SRAM and Separate FOUT(具有電池供電的8位SRAM和獨(dú)立輸出的低功率RTC) |
| 中文描述： | 低功耗RTC與8電池供電SRAM和獨(dú)立的FOUT（具有電池供電的8位的SRAM和獨(dú)立輸出的低功率實(shí)時(shí)時(shí)鐘字節(jié)） |
| 文件頁數(shù)： | 4/20頁 |
| 文件大小： | 328K |
| 代理商： | ISL1220 |
4
FN6315.0
June 22, 2006
V
IH
SDA and SCL Input Buffer HIGH
Voltage
0.7 x
V
DD
0.05 x
V
DD
0
V
DD
+
0.3
V
Hysteresis SDA and SCL Input Buffer
Hysteresis
V
V
OL
SDA Output Buffer LOW Voltage,
Sinking 3mA
0.4
V
Cpin
SDA and SCL Pin Capacitance
T
A
= 25°C, f = 1MHz, V
DD
= 5V, V
IN
= 0V,
V
OUT
= 0V
10
pF
f
SCL
t
IN
SCL Frequency
400
kHz
Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the max spec is
suppressed.
50
ns
t
AA
SCL Falling Edge to SDA Output
Data Valid
SCL falling edge crossing 30% of V
DD
, until
SDA exits the 30% to 70% of V
DD
window.
SDA crossing 70% of V
DD
during a STOP
condition, to SDA crossing 70% of V
DD
during the following START condition.
900
ns
t
BUF
Time the Bus Must be Free before
the Start of a New Transmission
1300
ns
t
LOW
t
HIGH
t
SU:STA
Clock LOW Time
Measured at the 30% of V
DD
crossing.
Measured at the 70% of V
DD
crossing.
SCL rising edge to SDA falling edge. Both
crossing 70% of V
DD
.
From SDA falling edge crossing 30% of V
DD
to SCL falling edge crossing 70% of V
DD
.
From SDA exiting the 30% to 70% of V
DD
window, to SCL rising edge crossing 30% of
V
DD
From SCL falling edge crossing 30% of V
DD
to SDA entering the 30% to 70% of V
DD
window.
1300
ns
Clock HIGH Time
600
ns
START Condition Setup Time
600
ns
t
HD:STA
START Condition Hold Time
600
ns
t
SU:DAT
Input Data Setup Time
100
ns
t
HD:DAT
Input Data Hold Time
0
900
ns
t
SU:STO
STOP Condition Setup Time
From SCL rising edge crossing 70% of V
DD
,
to SDA rising edge crossing 30% of V
DD
.
From SDA rising edge to SCL falling edge.
Both crossing 70% of V
DD
.
From SCL falling edge crossing 30% of V
DD
,
until SDA enters the 30% to 70% of V
DD
window.
600
ns
t
HD:STO
STOP condItion Hold Time
600
ns
t
DH
Output Data Hold Time
0
ns
t
R
SDA and SCL Rise Time
From 30% to 70% of V
DD
20 +
0.1 x Cb
300
ns
6
t
F
SDA and SCL Fall Time
From 70% to 30% of V
DD
20 +
0.1 x Cb
300
ns
6
Cb
Capacitive Loading of SDA or SCL
Total on-chip and off-chip
10
400
pF
6
Rpu
SDA and SCL Bus Pull-up Resistor
Off-chip
Maximum is determined by t
R
and t
F
.
For Cb = 400pF, max is about 2~2.5k
.
For Cb = 40pF, max is about 15~20k
1
k
6
NOTES:
2. IRQ and F
OUT
Inactive.
3. LPMODE = 0 (default).
4. In order to ensure proper timekeeping, the V
DD SR-
specification must be followed.
5. Typical values are for T = 25°C and 3.3V supply voltage.
6. These are I
2
C specific parameters and are not directly tested, however they are used during device testing to validate device specification.
7. A write to register 08h should only be done if V
DD
> V
BAT
, otherwise the device will be unable to communicate using I
2
C.
Serial Interface Specifications
Over the recommended operating conditions unless otherwise specified.
(Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 5)
MAX
UNITS
NOTES
ISL1220
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