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參數(shù)資料
| 型號(hào)： | ISL1208 |
| 廠商： | Intersil Corporation |
| 英文描述： | I2C Real Time Clock/Calendar(I2C實(shí)時(shí)時(shí)鐘/日歷) |
| 中文描述： | 的I2C實(shí)時(shí)時(shí)鐘/日歷（的I2C實(shí)時(shí)時(shí)鐘/日歷） |
| 文件頁(yè)數(shù)： | 4/21頁(yè) |
| 文件大?。?/td> | 349K |
| 代理商： | ISL1208 |
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4
FN8085.5
August 23, 2006
Cpin
SDA and SCL Pin Capacitance
T
A
= 25°C, f = 1MHz, V
DD
= 5V,
V
IN
= 0V, V
OUT
= 0V
10
pF
f
SCL
SCL Frequency
400
kHz
t
IN
Pulse width Suppression Time at SDA
and SCL Inputs
Any pulse narrower than the max spec
is suppressed.
50
ns
t
AA
SCL Falling Edge to SDA Output Data
Valid
SCL falling edge crossing 30% of V
DD
,
until SDA exits the 30% to 70% of V
DD
window.
900
ns
t
BUF
Time the Bus Must Be Free Before the
Start of a New Transmission
SDA crossing 70% of V
DD
during a
STOP condition, to SDA crossing 70%
of V
DD
during the following START
condition.
1300
ns
t
LOW
Clock LOW Time
Measured at the 30% of V
DD
crossing.
1300
ns
t
HIGH
Clock HIGH Time
Measured at the 70% of V
DD
crossing.
600
ns
t
SU:STA
START Condition Setup Time
SCL rising edge to SDA falling edge.
Both crossing 70% of V
DD
.
600
ns
t
HD:STA
START Condition Hold Time
From SDA falling edge crossing 30% of
V
DD
to SCL falling edge crossing 70%
of V
DD
.
600
ns
t
SU:DAT
Input Data Setup Time
From SDA exiting the 30% to 70% of
V
DD
window, to SCL rising edge
crossing 30% of V
DD
100
ns
t
HD:DAT
Input Data Hold Time
From SCL falling edge crossing 30% of
V
DD
to SDA entering the 30% to 70%
of V
DD
window.
20
900
ns
t
SU:STO
STOP Condition Setup Time
From SCL rising edge crossing 70% of
V
DD
, to SDA rising edge crossing 30%
of V
DD
.
600
ns
t
HD:STO
STOP Condition Hold Time
From SDA rising edge to SCL falling
edge. Both crossing 70% of V
DD
.
600
ns
t
DH
Output Data Hold Time
From SCL falling edge crossing 30% of
V
DD
, until SDA enters the 30% to 70%
of V
DD
window.
0
ns
t
R
SDA and SCL Rise Time
From 30% to 70% of V
DD
20 +
0.1 x Cb
300
ns
t
F
SDA and SCL Fall Time
From 70% to 30% of V
DD
20 +
0.1 x Cb
300
ns
Cb
Capacitive Loading of SDA or SCL
Total on-chip and off-chip
10
400
pF
Rpu
SDA and SCL Bus Pull-Up Resistor
Off-Chip
Maximum is determined by t
R
and t
F
.
For Cb = 400pF, max is about 2~2.5k
.
For Cb = 40pF, max is about 15~20k
1
k
NOTES:
1. IRQ & F
OUT
Inactive.
2. LPMODE = 0 (default).
3. In order to ensure proper timekeeping, the V
DD SR-
specification must be followed.
4. Typical values are for T = 25°C and 3.3V supply voltage.
Serial Interface Specifications
Over the recommended operating conditions unless otherwise specified.
(Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 4)
MAX
UNITS
NOTES
ISL1208
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