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參數(shù)資料
| 型號： | ISL1208 |
| 廠商： | Intersil Corporation |
| 英文描述： | I2C Real Time Clock/Calendar(I2C實時時鐘/日歷) |
| 中文描述： | 的I2C實時時鐘/日歷（的I2C實時時鐘/日歷） |
| 文件頁數(shù)： | 15/21頁 |
| 文件大?。?/td> | 349K |
| 代理商： | ISL1208 |
15
FN8085.5
August 23, 2006
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (See Figure 13).
The ISL1208 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL1208 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation.
FIGURE 12. VALID DATA CHANGES, START, AND STOP CONDITIONS
FIGURE 13. ACKNOWLEDGE RESPONSE FROM RECEIVER
FIGURE 14. BYTE WRITE SEQUENCE
SDA
SCL
START
DATA
STABLE
DATA
CHANGE
STOP
DATA
STABLE
SDA OUTPUT FROM
TRANSMITTER
SDA OUTPUT FROM
RECEIVER
8
1
9
START
ACK
SCL FROM
MASTER
HIGH IMPEDANCE
HIGH IMPEDANCE
S
T
A
R
T
S
T
O
P
IDENTIFICATION
BYTE
DATA
BYTE
A
C
K
SIGNALS FROM
THE MASTER
SIGNALS FROM
THE ISL1208
A
C
K
1
0
0
1
1
A
C
K
WRITE
SIGNAL AT SDA
0 0 0 0
1 1 1
ADDRESS
BYTE
ISL1208
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