4 FN6682.3 December 6, 2011 Power-Down Timing Test Conditions: VDD = +2.7 to +5.5V, TA = -40°C" />
參數(shù)資料
型號(hào)： ISL12023IVZ
廠商： Intersil
文件頁(yè)數(shù)： 24/29頁(yè)
文件大小： 0K
描述： IC RTC/CLDR TEMP SNSR 14-TSSOP
產(chǎn)品培訓(xùn)模塊： Solutions for Industrial Control Applications
標(biāo)準(zhǔn)包裝： 960
類(lèi)型： 時(shí)鐘/日歷
特點(diǎn)： 警報(bào)器，夏令時(shí)，閏年，SRAM
存儲(chǔ)容量： 128B
時(shí)間格式： HH:MM:SS（12/24 小時(shí)）
數(shù)據(jù)格式： YY-MM-DD-dd
接口： I²C，2 線串口
電源電壓： 2.7 V ~ 5.5 V
電壓 - 電源，電池： 1.8 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 14-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 14-TSSOP
包裝： 管件
ISL12023
4
FN6682.3
December 6, 2011
Power-Down Timing Test Conditions: VDD = +2.7 to +5.5V, TA = -40°C to +85°C, unless otherwise stated.
SYMBOL
PARAMETER
CONDITIONS
MIN
(Note 11)
TYP
(Note 7)
MAX
(Note 11)
UNITS
NOTES
VDD SR-
VDD Negative Slew Rate
10
V/ms
VDDSR+
VDD Positive Slew Rate, Minimum
0.05
V/ms
I2C Interface Specifications Test Conditions: VDD = +2.7 to +5.5V, TA = -40°C to +85°C, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 11)
TYP
(Note 7)
MAX
(Note 11)
UNITS
NOTES
VIL
SDA and SCL Input Buffer LOW
Voltage
-0.3
0.3 x VDD
V
VIH
SDA and SCL Input Buffer HIGH
Voltage
0.7 x VDD
VDD + 0.3
V
Hysteresis
SDA and SCL Input Buffer Hysteresis
0.05 x VDD
VOL
SDA Output Buffer LOW Voltage,
Sinking 3mA
VDD = 5V, IOL = 3mA
0
0.02
0.4
V
CPIN
SDA and SCL Pin Capacitance
TA = +25°C, f = 1MHz,
VDD = 5V, VIN = 0V,
VOUT = 0V
10
pF
9, 10
fSCL
SCL Frequency
400
kHz
tIN
Pulse Width Suppression Time at SDA
and SCL Inputs
Any pulse narrower than the
max spec is suppressed.
50
ns
tAA
SCL Falling Edge To SDA Output Data
Valid
SCL falling edge crossing 30%
of VDD, until SDA exits the 30%
to 70% of VDD window.
900
ns
tBUF
Time the Bus must be Free Before the
Start of a New Transmission
SDA crossing 70% of VDD
during a STOP condition, to SDA
crossing 70% of VDD during the
following START condition.
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VDD
crossing.
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VDD
crossing.
600
ns
tSU:STA
START Condition Setup Time
SCL rising edge to SDA falling
edge. Both crossing 70% of
VDD.
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing
30% of VDD to SCL falling edge
crossing 70% of VDD.
600
ns
tSU:DAT
Input Data Setup Time
From SDA exiting the 30% to
70% of VDD window, to SCL
rising edge crossing 30% of
VDD.
100
ns
tHD:DAT
Input Data Hold Time
From SCL falling edge crossing
30% of VDD to SDA entering the
30% to 70% of VDD window.
0
900
ns
tSU:STO
STOP Condition Setup Time
From SCL rising edge crossing
70% of VDD, to SDA rising edge
crossing 30% of VDD.
600
ns
tHD:STO
STOP Condition Hold Time
From SDA rising edge to SCL
falling edge. Both crossing 70%
of VDD.
600
ns
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