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參數(shù)資料
| 型號： | ISL12023IVZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 11/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC/CLDR TEMP SNSR 14-TSSOP |
| 產品培訓模塊： | Solutions for Industrial Control Applications |
| 標準包裝： | 960 |
| 類型： | 時鐘/日歷 |
| 特點： | 警報器，夏令時，閏年，SRAM |
| 存儲容量： | 128B |
| 時間格式： | HH:MM:SS（12/24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 14-TSSOP |
| 包裝： | 管件 |
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ISL12023
19
FN6682.3
December 6, 2011
There are two alarm operation modes: Single Event and periodic
Interrupt Mode:
Single Event Mode is enabled by setting the bit 7 on any of the
Alarm registers (ESCA0... EDWA0) to “1”, the IM bit to “0”, and
disabling the frequency output. This mode permits a one-time
match between the Alarm registers and the RTC registers.
Once this match occurs, the ALM bit is set to “1” and the IRQ
output will be pulled low and will remain low until the ALM bit
is reset. This can be done manually or by using the auto-reset
feature.
Interrupt Mode is enabled by setting the bit 7 on any of the
Alarm registers (ESCA0... EDWA0) to “1”, the IM bit to “1”, and
disabling the frequency output. The IRQ output will now be
pulsed each time an alarm occurs. This means that once the
interrupt mode alarm is set, it will continue to alarm for each
occurring match of the alarm and present time. This mode is
convenient for hourly or daily hardware interrupts in
microcontroller applications such as security cameras or utility
meter reading.
To clear a single event alarm, the ALM bit in the status register
must be set to “0” with a write. Note that if the ARST bit is set to
1 (address 08h, bit 7), the ALM bit will automatically be cleared
when the status register is read.
Following are examples of both Single Event and periodic
Interrupt Mode alarms.
Example 1
Alarm set with single interrupt (IM = “0”)
A single alarm will occur on January 1 at 11:30 a.m.
Set Alarm registers as follows:
After these registers are set, an alarm will be generated when the
RTC advances to exactly 11:30 a.m. on January 1 (after seconds
changes from 59 to 00) by setting the ALM bit in the status register
to “1” and also bringing the IRQ output low.
Example 2
Pulsed interrupt once per minute (IM = “1”)
Interrupts at one minute intervals when the seconds register is
at 30s.
Set Alarm registers as follows:
Once the registers are set, the following waveform will be seen at
IRQ:
Note that the status register ALM bit will be set each time the
alarm is triggered, but does not need to be read or cleared.
Time Stamp VDD to Battery Registers (TSV2B)
The TSV2B Register bytes are identical to the RTC register bytes,
except they do not extend beyond the Month. The Time Stamp
captures the FIRST VDD to Battery Voltage transition time, and will
not update upon subsequent events, until cleared (only the first
event is captured before clearing). Set CLRTS = 1 to clear this
register (Add 09h, PWR_VDD register).
Note that the time stamp registers are cleared to all “0”,
including the month and day, which is different from the RTC and
alarm registers (those registers default to 01h). This is the
indicator that no time stamping has occurred since the last clear
or initial power-up. Once a time stamp occurs, there will be a non-
zero time stamp.
Time Stamp Battery to VDD Registers (TSB2V)
The Time Stamp Battery to VDD Register bytes are identical to
the RTC register bytes, except they do not extend beyond Month.
The Time Stamp captures the LAST transition of VBAT to VD (only
the last event of a series of power-up/down events is retained).
Set CLRTS = 1 to clear this register (add 09h, PWR_VDD register).
ALARM
REGISTER
BIT
DESCRIPTION
765 4321 0
HEX
SCA0
000 000 00
00h
Seconds disabled
MNA0
101 100 00
B0h
Minutes set to 30,
enabled
HRA0
100 100 01
91h
Hours set to 11,
enabled
DTA0
100 000 01
81h
Date set to 1,
enabled
MOA0
100 000 01
81h
Month set to 1,
enabled
DWA0
000 000 00
00h
Day of week
disabled
TABLE 21.
ALARM
REGISTER
BIT
DESCRIPTION
76 54 32 10
HEX
SCA0
10 11 00 00
B0h Seconds set to 30,
enabled
MNA0
00 00 00 00
00h Minutes disabled
HRA0
00 00 00 00
00h Hours disabled
DTA0
00 00 00 00
00h Date disabled
MOA0
00 00 00 00
00h Month disabled
DWA0
00 00 00 00
00h Day of week
disabled
60s
RTC AND ALARM REGISTERS ARE BOTH “30s”
FIGURE 13. IRQ WAVEFORM
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