26 FN7576.3 June 7, 2012 An acknowledge (ACK) is a software convention used to indicate a successful data transfer. The transmit" />
參數(shù)資料
型號: ISL12022MIBZR5421
廠商: Intersil
文件頁數(shù): 19/31頁
文件大小: 0K
描述: IC RTC/CALENDAR TEMP SNSR 20SOIC
應用說明: Addressing Power Issues in Real Time Clock Appls
產品培訓模塊: Solutions for Industrial Control Applications
標準包裝: 760
類型: 時鐘/日歷
特點: 警報器,夏令時,閏年,SRAM
存儲容量: 128B
時間格式: HH:MM:SS(12/24 小時)
數(shù)據格式: YY-MM-DD-dd
接口: I²C,2 線串口
電源電壓: 2.7 V ~ 5.5 V
電壓 - 電源,電池: 1.8 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
供應商設備封裝: 20-SOIC
包裝: 管件
ISL12022MR5421
26
FN7576.3
June 7, 2012
An acknowledge (ACK) is a software convention used to indicate
a successful data transfer. The transmitting device, either master
or slave, releases the SDA bus after transmitting eight bits.
During the ninth clock cycle, the receiver pulls the SDA line LOW
to acknowledge the reception of the eight bits of data (see Figure
The ISL12022MR5421 responds with an ACK after recognition of
a START condition followed by a valid Identification Byte, and
once again, after successful receipt of an Address Byte. The
ISL12022MR5421 also responds with an ACK after receiving a
Data Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation.
Device Addressing
Following a start condition, the master must output a Slave Address
Byte. The 7 MSBs are the device identifiers. These bits are
“1101111” for the RTC registers and “1010111” for the User SRAM.
The last bit of the Slave Address Byte defines a read or write
operation to be performed. When this R/W bit is a “1”, a read
operation is selected. A “0” selects a write operation (refer to
Figure 20).
After loading the entire Slave Address Byte from the SDA bus, the
ISL12022MR5421 compares the device identifier and device select
bits with “1101111” or “1010111”. Upon a correct compare, the
device outputs an acknowledge on the SDA line.
Following the Slave Byte is a one byte word address. The word
address is either supplied by the master device or obtained from an
internal counter. On power-up, the internal address counter is set to
address 00h, so a current address read starts at address 00h. When
required, as part of a random read, the master must supply the 1
Word Address Bytes, as shown in Figure 22.
In a random read operation, the slave byte in the “dummy write”
portion must match the slave byte in the “read” section. For a
random read of the Control/Status Registers, the slave byte must be
“1101111x” in both places.
Write Operation
A Write operation requires a START condition, followed by a valid
Identification Byte, a valid Address Byte, a Data Byte, and a STOP
condition. After each of the three bytes, the ISL12022MR5421
responds with an ACK. At this time, the I2C interface enters a
standby state.
Read Operation
A Read operation consists of a three byte instruction, followed by
one or more Data Bytes (see Figure 22). The master initiates the
operation issuing the following sequence: a START, the
FIGURE 18. ACKNOWLEDGE RESPONSE FROM RECEIVER
FIGURE 19. BYTE WRITE SEQUENCE (SLAVE ADDRESS FOR CSR SHOWN)
SDA OUTPUT FROM
TRANSMITTER
SDA OUTPUT FROM
RECEIVER
8
1
9
START
ACK
SCL FROM
MASTER
HIGH IMPEDANCE
S
T
A
R
T
S
T
O
P
IDENTIFICATION
BYTE
DATA
BYTE
A
C
K
SIGNALS FROM THE
MASTER
SIGNALS FROM THE
ISL12022MR5421
A
C
K
10
0
11
A
C
K
WRITE
SIGNAL AT SDA
00 00
111
ADDRESS
BYTE
FIGURE 20. SLAVE ADDRESS, WORD ADDRESS AND DATA BYTES
SLAVE ADDRESS
BYTE
D7
D6
D5
D2
D4
D3
D1
D0
A0
A7
A2
A4
A3
A1
DATA BYTE
A6
A5
1
10
1
R/W
1
WORD ADDRESS
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