參數資料
| 型號： | ISL12020MIRZ-T7A |
| 廠商： | Intersil |
| 文件頁數： | 33/34頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC/CALENDAR TEMP SNSR 20DFN |
| 產品培訓模塊： | Solutions for Industrial Control Applications |
| 標準包裝： | 250 |
| 類型： | 時鐘/日歷 |
| 特點： | 警報器，夏令時，閏年，SRAM |
| 存儲容量： | 128B |
| 時間格式： | HH:MM:SS（12/24 小時） |
| 數據格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-LFDFN 裸露焊盤 |
| 供應商設備封裝： | 20-DFN（5.5x4.0） |
| 包裝： | 帶卷 (TR) |
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ISL12020M
8
FN6667.5
December 13, 2011
tHD:STA
START Condition Hold Time
From SDA falling edge
crossing 30% of VDD to SCL
falling edge crossing 70% of
VDD.
600
ns
tSU:DAT
Input Data Setup Time
From SDA exiting the 30% to
70% of VDD window, to SCL
rising edge crossing 30% of
VDD.
100
ns
tHD:DAT
Input Data Hold Time
From SCL falling edge
crossing 30% of VDD to SDA
entering the 30% to 70% of
VDD window.
20
900
ns
tSU:STO
STOP Condition Setup Time
From SCL rising edge
crossing 70% of VDD, to SDA
rising edge crossing 30% of
VDD.
600
ns
tHD:STO
STOP Condition Hold Time
From SDA rising edge to SCL
falling edge. Both crossing
70% of VDD.
600
ns
tDH
Output Data Hold Time
From SCL falling edge
crossing 30% of VDD, until
SDA enters the 30% to 70%
of VDD window.
0
ns
tR
SDA and SCL Rise Time
From 30% to 70% of VDD.
20 + 0.1 x Cb
300
ns
tF
SDA and SCL Fall Time
From 70% to 30% of VDD.
20 + 0.1 x Cb
300
ns
Cb
Capacitive Loading of SDA or SCL Total on-chip and off-chip
10
400
pF
RPU
SDA and SCL Bus Pull-up Resistor
Off-chip
Maximum is determined by
tR and tF.
For Cb = 400pF, max is
about 2k
~2.5k.
For Cb = 40pF, max is about
15k
~20k
1
k
NOTES:
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
9. Specified at +25°C.
10. Minimum VDD and/or VBAT of 1V to sustain the SRAM. The value is based on characterization and it is not tested.
11. Temperature Conversion is inactive below VBAT = 2.7V. Device operation is not guaranteed at VBAT<1.8V.
12. IRQ/FOUT Inactive.
13. VDD > VBAT +VBATHYS
14. In order to ensure proper timekeeping, the VDD SR- specification must be followed.
15. Limits should be considered typical and are not production tested.
16. These are I2C specific parameters and are not tested, however, they are used to set conditions for testing devices to validate
specification.
17. To avoid EEPROM recall issues, it is advised to use this minimum power up slew rate. Not tested, shown as typical only.
I2C Interface Specifications Test Conditions: VDD = +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise specified.
Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 8)
TYP (Note 9)
MAX
(Note 8)
UNITS
NOTES
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