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參數(shù)資料
| 型號： | ISAC-SX |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | ISDN SUBSCRIBER ACCESS CONTROLLER |
| 中文描述： | ISDN用戶接入控制器 |
| 文件頁數(shù)： | 199/262頁 |
| 文件大?。?/td> | 3476K |
| 代理商： | ISAC-SX |
ISAC-SX
PEB 3086
Detailed Register Description
Data Sheet
199
2003-01-30
DPS_D ... Data Port Selection for D-Channel Timeslot access
0: The B-channel controller data is output on DD.
The B-channel controller data is input from DU.
1: The B-channel controller data is output on DU.
The B-channel controller data is input from DD.
EN_D ... Enable D-Channel Timeslot (2-bit) for B-Channel controller access
EN_BC2 ... Enable B2-Channel Timeslot (8-bit) for B-Channel controller access
EN_BC1 ... Enable B1-Channel Timeslot (8-bit) for B-Channel controller access
These bits individually enable/disable the B-channel access to the 2-bit and the two 8-bit
timeslots.
0: B-channel B/A does not access timeslot data B1, B2 or D, respectively.
1: B-channel B/A does access timeslot data B1, B2 or D, respectively.
Note: The terms B1/B2 should not imply that the 8-bit timeslots must be located in the
first/second IOM-2 timeslots, it’s simply a placeholder for the 8-bit timeslot position
selected in the registers BCH_TSDP_BC1/2.
CS2-0 ... Channel Select for D-Channel Timeslot access
This register is used to select one of eight IOM channels. If enabled (EN_D=1), the
B-channel controller is connected to the 2-bit D-channel timeslot of that IOM channel.
Note: The reset value is determined by the channel select pins CH2-0 which are directly
mapped to CS2-0.
4.4.6
DCI_CR - Control Register for D and CI1 Handler
(IOM_CR.CI_CS=0)
Value after reset: A0
H
Read and write access to this register is only possible if IOM_CR.CI_CS = 0.
DPS_CI1 ... Data Port Selection CI1 Handler Data
0: The CI1 handler data is output on DD and input from DU
1: The CI1 handler data is output on DU and input from DD
7
0
DCI_CR
DPS_
CI1
EN_
CI1
D_
EN_D
D_
EN_B2
D_
EN_B1
CS2-0
RD/WR (53)
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