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參數(shù)資料
| 型號： | IS82C85 |
| 廠商： | INTERSIL CORP |
| 元件分類： | XO, clock |
| 英文描述： | CMOS Static Clock Controller/Generator |
| 中文描述： | 8 MHz, PROC SPECIFIC CLOCK GENERATOR, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 3/21頁 |
| 文件大小： | 363K |
| 代理商： | IS82C85 |
299
Functional Block Diagram
RES
17
I
RESET IN: RES is an active LOW signal which is used to generate RESET. The 82C85 provides a
Schmitt trigger input so that an RC connection can be used to establish the power-up reset of proper
duration. RES starts crystal oscillator operation.
RESET
16
O
RESET: RESET is an active HIGH signal which is used to reset the 80C86 family processors. Its
timing characteristics are determined by RES. RESET is guaranteed to be HIGH for a minimum of
16 CLK pulses after the rising edge of RES.
CSYNC
1
I
CLOCK SYNCHRONIZATION: CSYNC is an active HIGH signal which allows multiple 82C85 and
82C84A to be synchronized to provide multiple in-phase clock signals When CSYNC is HIGH, the
internal counters are reset and force CLK, CLK50 and PCLK into a HIGH state. When CSYNC is
LOW, the internal counters are allowed to count and the CLK, CLK50 and PCLK outputs are active.
CSYNC must be externally synchronized to EFI.
AEN1
AEN2
3
7
I
I
ADDRESS ENABLE: AEN is an active LOW signal. AEN serves to qualify its respective Bus Ready
Signal (RDY1 or RDY2). AEN1 validates RDY1 while AEN2 validates RDY2. Two AEN signal inputs
are useful in system configurations which permit the processor to access two Multi-Master System
Buses.
RDY1
RDY2
4
6
I
I
BUS READY: (Transfer Complete). RDY is an active HIGH signal which is an indication from a de-
vice located on the system data bus that data has been received, or is available RDY1 is qualified
by AEN1 while RDY2 is qualified by AEN2.
ASYNC
21
I
READY SYNCHRONIZATION SELECT: ASYNC is an input which defines the synchronization
mode of the READY logic. When ASYNC is LOW, two stages of READY synchronization are pro-
vided. When ASYNC is left open or HIGH a single stage of READY synchronization is provided.
READY
5
O
READY: READY is an active HIGH signal which is the synchronized RDY signal input.
GND
9
I
Ground
V
CC
24
I
V
CC
: is the +5V power supply pin. A 0.1mF capacitor between V
CC
and GND is recommended.
Pin Descriptions
(Continued)
SYMBOL
DIP PIN
NUMBER
TYPE
DESCRIPTION
STOP LOGIC
SYNC
LOGIC
PERIPHERAL
CLOCK
(DIVIDE BY 6)
READY
SYNC
OSCILLATOR
READY
SELECT
SPEED SELECT
DIV 256 OR DIV 1
RESTART
LOGIC
CLOCK
LOGIC
(DIVIDE
BY 3)
RESET PULSE
CONDITIONING
LOGIC
RESET
CLK
CLK50
PCLK
OSC
READY
(16)
(8)
(10)
(2)
(18)
(5)
(17)
(1)
(12)
(19)
(23)
(21)
(11)
(20)
(22)
(15)
(14)
(13)
(4)
(3)
(7)
(6)
RES
START
CSYNC
SLO/FST
F/C
EFI
X2
X1
S2/STOP
S1
S0
RDY1
AEN1
AEN2
RDY2
ASYNC
RESTART
SYNC
MASTER
OSC
SELECTED
OSC
HALT
V
CC
(24)
GND (9)
O
EXTERNAL
FREQ.
SELECT
82C85
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