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參數(shù)資料
| 型號： | IS82C85 |
| 廠商： | INTERSIL CORP |
| 元件分類： | XO, clock |
| 英文描述： | CMOS Static Clock Controller/Generator |
| 中文描述： | 8 MHz, PROC SPECIFIC CLOCK GENERATOR, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 12/21頁 |
| 文件大?。?/td> | 363K |
| 代理商： | IS82C85 |
308
(27)
TCLCH
CLK LOW Time
(2/3 TCLCL)-15
-
ns
(28)
T5CHCL
CLK50 HIGH Time
(1/2 TCLCL)-7.5
-
ns
(29)
T5CLCH
CLK50 LOW Time
(1/2 TCLCL)-7.5
-
ns
(30)
TCH1CH2
CLK/CLK50 Rise Time
-
8
ns
1.0V to 3.5V
(31)
TCL2CL1
CLK/CLK50 Fall Time
-
8
ns
1.0V to 3.5V
(32)
TPHPL
PCLK HIGH Time
TCLCL-20
-
ns
(33)
TPLPH
PCLK LOW Time
TCLCL-20
-
ns
(34)
TRYLCL
Ready Inactive to CLK
-8
-
ns
Note 4
(35)
TRYHCH
Ready Active to CLK
2/3(TCLCL)-15
-
ns
Note 3
(36)
TCLIL
CLK to Reset Delay
-
40
ns
(37)
TCLPH
CLK to PCLK HIGH Delay
-
22
ns
(38)
TCLPL
CLK to PCLK LOW Delay
-
22
ns
(39)
TOST
Start/Reset Valid to Clock LOW
-
2
ms
Typ. - Note 8
(40)
TOLOH
Output Rise Time (except CLK)
-
15
ns
From 0.8V to 2.0V
(41)
TOHOL
Output Fall Time (except CLK)
-
12
ns
From 2.0V to 0.8V
(42)
TRST
RESET output HIGH Time
16 x TCLCL
-
ns
(43)
TCLC50L
CLK LOW to CLK50 LOW Skew
-
5
ns
NOTES:
1. Slow and Fast Modes.
2. Setup and hold necessary only to guarantee recognition at next clock.
3. Applies only to T3, TW states.
4. Applies only to T2 states.
5. All timing delays are measured at 1.5V unless otherwise noted.
6. Input signals must switch between V
IL
max - 0.4 and V
IH
min + 0.4 volts
7. Timing measurements made with EFI duty cycle = 50%.
8. Oscillator start up time depends on several factors including crystal frequency, crystal manufacturer, capacitive load, temperature, power
supply voltage, etc. This parameter is given for information only.
9. Output signals switch between V
OH
and V
OL
unless otherwise specified.
AC Electrical Specifications
V
CC
= 5V
±
10%;T
A
= 0
o
C to +70
o
C (C82C85);
T
A
= -40
o
C to +85
o
C (I82C85);
T
A
= -55
o
C to +125
o
C (M82C85)
(Continued)
SYMBOL
PARAMETER
LIMITS
UNITS
CONDITIONS
MIN
MAX
82C85
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