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參數(shù)資料
| 型號： | IS82C50A-5Z |
| 廠商： | Intersil |
| 文件頁數(shù)： | 25/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PERIPH UART/BRG 10MHZ 44-PLCC |
| 標(biāo)準(zhǔn)包裝： | 26 |
| 特點(diǎn)： | 單芯片 UART/BRG |
| 通道數(shù)： | 1，UART |
| 規(guī)程： | RS232C |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 帶并行端口： | 是 |
| 帶故障啟動(dòng)位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC |
| 包裝： | 管件 |
9
FN2958.5
August 24, 2006
82C50A
The contents of the Line Status Register are indicated in the
above table and are described below.
LSR(0) Data Ready (DR): Data Ready is set high when an
incoming character has been received and transferred into
the Receiver Buffer Register. LSR(0) is reset low by a CPU
read of the data in the Receiver Buffer Register.
LSR(1) Overrun Error (OE): Overrun Error indicates that
data in the Receiver Buffer Register was not read by the
CPU before the next character was transferred into the
Receiver Buffer Register, overwriting the previous character.
The OE indicator is reset whenever the CPU reads the
contents of the Line Status Register.
LSR(2) Parity Error (PE): Parity Error indicates that the
received data character does not have the correct even or
odd parity, as selected by the Even Parity Select bit (LCR
(4)). The PE bit is set high upon detection of a parity error,
and is reset low when the CPU reads the contents of the
LSR.
LSR(3) Framing Error (FE): Framing Error indicates that
the received character did not have a valid stop bit. LSR(3)
is set high when the stop bit following the last data bit or
parity bit is detected as a zero bit (spacing level). The FE
indicator is reset low when the CPU reads the contents of
the LSR.
LSR(4) Break Interrupt (BI): Break Interrupt is set high
when the received data input is held in the spacing (logic 0)
state for longer than a full word transmission time (start bit +
data bits + parity + stop bits). The B indicator is reset when
the CPU reads the contents of the Line Status Register.
LSR(1) - LSR(4) are the error conditions that produce a
Receiver Line Status interrupt (priority 1 interrupt in the
Interrupt Identification Register (IIR)) when any of the
conditions are detected. This interrupt is enabled by setting
lER (2) = 1 in the Interrupt Enable Register.
LSR(5) Transmitter Holding Register Empty
(THRE): THRE indicates that the 82C50A is ready to accept
a new character for transmission. The THRE bit is set high
when a character is transferred from the Transmitter Holding
Register into the Transmitter Shift Register. LSR(5) is reset
low by the loading of the Transmitter Holding Register by the
CPU. LSR(5) is not reset by a CPU read of the LSR.
When the THRE interrupt is enabled (IER(1) = 1), THRE
causes a priority 3 interrupt in the lIR. If THRE is the interrupt
source indicated in IIR, lNTRPT is cleared by a read of the
IIR.
LSR(6) Transmitter Empty (TEMT): TEMT is set high
when the Transmitter Holding Register (THR) and the
Transmitter Shift Register (TSR) are both empty. LSR(6) is
reset low when a character is loaded into the THR and
remains low until the character is transferred out of SOUT.
TEMT is not reset low by a CPU read of the LSR.
LSR(7): This bit is permanently set to logic 0.
MODEM CONTROL REGISTER (MCR)
The MCR controls the interface with the modem or data set
as described below. The MCR can be written and read. The
RTS, DTR, OUT1 and OUT2 outputs are directly controlled
by their control bits in this register. A high input asserts a
low (true) at the output pins.
MCR(0): When MCR(0) is set high, the DTR output is forced
low. When MCR(0) is reset low, the DTR output is forced
high. The DTR output of the 82C50A may be input into an
ElA inverting line driver as the 1488 to obtain the proper
polarity input at the modem or data set.
MCR(1): When MCR(1) is set high, the RTS output is forced
low. When MCR(1) is reset low, the RTS output is forced
high. The RTS output of the 82C50A may be input into an
ElA inverting line driver as the 1488 to obtain the proper
polarity input at the modem or data set.
MCR(2): When MCR(2) is set high, the OUT1 output is
forced low. When MCR(2) is reset low, the OUT1 output is
forced high. OUT1 is an user designated output.
LSR BITS 0 THRU 7
LOGIC 1
LOGIC 0
LSR
(0) Data Ready (DR)
Ready
Not Ready
LSR
(1) Overrun Error (OE)
Error
No Error
LSR
(2) Parity Error (PE)
Error
No Error
LSR
(3) Framing Error (FE)
Error
No Error
LSR
(4) Break Interrupt (BI)
Break
No Break
LSR
(5) Transmitter Holding
Register Empty (THRE)
Empty
Not Empty
LSR
(6) Transmitter Empty (TEMT)
Empty
Not Empty
LSR
(7) Not Used
MCR BITS 0 THRU 7
MCR BIT
LOGIC 1
MCR BIT
LOGIC 0
MCR
(0) Data Terminal Ready
(DTR)
DTR
Output Low
DTR
Output High
MCR
(1) Request to Send
(RTS)
RTS
Output Low
RTS
Output High
MCR
(2) OUT1
OUT1
Output Low
OUT1
Output High
MCR
(3) OUT2
OUT2
Output Low
OUT2
Output High
MCR
(4) LOOP
LOOP
Enabled
LOOP
Disabled
MCR
(5) 0
MCR
(6) 0
MCR
(7) 0
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