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11
IRS2130/IRS21303/IRS2132 (J&S)PbF
1 PCB Layout Tips 
    1.1 Distance from H to L Voltage 
The IRS213(0,03,2)J package lacks some pins (see page 8) in order to maximizing the distance between the high 
voltage and low voltage pins. It’s strongly recommended to place the components tied to the floating voltage in the 
respective high voltage portions of the device (V
B1,2,3
, V
S1,2,3
) side.
1.2 Ground Plane 
To minimize noise coupling the ground plane must not be placed under or near the high voltage floating side.  
1.3 Gate Drive Loops 
Current loops behave like an antenna able to receive and transmit EM noise (see Fig. 7). In order to reduce EM 
coupling and improve the power switch turn on/off performances, gate drive loops must be reduced as much as 
possible. Moreover, current can be injected inside the gate drive loop via the IGBT collector-to-gate parasitic 
capacitance. The parasitic auto-inductance of the gate loop contributes to develop a voltage across the gate-emitter 
increasing the possibility of self turn-on effect.  
Fig. 7. Antenna Loops 
1.4 Supply Capacitors 
Supply capacitors must be placed as close as possible to the device pins (V
CC
 and V
SS
 for the ground tied supply, V
B
and V
S 
for the floating supply) in order to minimize parasitic inductance/resistance. 
1.5 Routing and Placement 
Power stage PCB parasitic may generate dangerous voltage transients for the gate driver and the control logic. In 
particular it’s recommended to limit phase voltage negative transients. 
In order to avoid such undervoltage it is highly recommended to minimize high side emitter to low side collector 
distance and low side emitter to negative bus rail stray inductance. See DT04-4 at 
www.irf.com
 for more detailed 
information. 
gate
resistance
V
SX
( Vs0 )
V
BX
 (V
CC
)
HO
X
 (LO
X
)
V
GE
Gate  Drive
 Loop
C
GC
I
GC
    PRELIMINARY