
IRMCK203
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Table of Figures
Figure 1: IRMCS2031 Simplified Blocks.........................................................................................................................7
Figure 2: Input/Output of IRMCK203..............................................................................................................................8
Figure 3: Application Connection of IRMCK203...........................................................................................................12
Figure 4: Oscillator Circuit .............................................................................................................................................13
Figure 5: PLL Low Pass Filter Shielding........................................................................................................................14
Figure 6: System Level SYNC To SYNC Timing..........................................................................................................22
Figure 7: FAULT and REDLED Response to GATEKILL............................................................................................23
Figure 8: SPI Timing.......................................................................................................................................................24
Figure 9: Host Parallel Read Cycle.................................................................................................................................25
Figure 10: Host Parallel Write Cycle..............................................................................................................................26
Figure 11: Discrete I/O Timing.......................................................................................................................................27
Figure 12: PWM Timing.................................................................................................................................................28
Figure 13: IR2175 Interface............................................................................................................................................28
Figure 14: Top Level ADC Timing ................................................................................................................................29
Table of Tables
Table 1: Typical Values for the Clock Circuit................................................................................................................13
Table 2: PLL Test Pin Assignments................................................................................................................................14
Table 3: PLL Low Pass Filter Values.............................................................................................................................15
Table 4: Absolute Maximum Ratings .............................................................................................................................16
Table 5: Recommended Operating Conditions...............................................................................................................16
Table 6: DC Characteristics............................................................................................................................................17
Table 7: Non Schmitt Input Characteristics....................................................................................................................17
Table 8: Schmitt Input Characteristics............................................................................................................................17
Table 9: Output Characteristics.......................................................................................................................................17
Table 10: Output Characteristics OSC2CLK..................................................................................................................18
Table 11: Pin and I/O Characteristics .............................................................................................................................21
Table 12: IRMCK203 Power Consumption....................................................................................................................21
Table 13: System Level SYNC to SYNC Timing...........................................................................................................22
Table 14: FAULT and REDLED Response to GATEKILL...........................................................................................23
Table 15: SPI Timing......................................................................................................................................................24
Table 16: Host Parallel Read Cycle Timing....................................................................................................................25
Table 17: Host Parallel Write Cycle Timing...................................................................................................................26