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| 型號(hào)： | IQ80C52XXX-16SHXXX:RD |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQFP44 |
| 文件頁數(shù)： | 4/60頁 |
| 文件大?。?/td> | 5137K |
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12
8266D-MCU Wireless-06/12
ATmega128RFA1
stored when entering an interrupt routine and restored when returning from an interrupt
routine. This must be handled by software.
7.5 General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to
achieve the required performance and flexibility, the following input/output schemes are
supported by the Register File:
One 8-bit output operand and one 8-bit result input
Two 8-bit output operands and one 8-bit result input
Two 8-bit output operands and one 16-bit result input
One 16-bit output operand and one 16-bit result input
Figure 7-1 below shows the structure of the 32 general purpose working registers in the
CPU.
Figure 7-1. AVR CPU General Purpose Working Registers
Most of the instructions operating on the Register File have direct access to all
registers, and most of them are single cycle instructions.
As shown in Figure 7-1 above each register is also assigned a data memory address,
mapping them directly into the first 32 locations of the user Data Space. Although not
being physically implemented as SRAM locations, this memory organization provides
great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be
set to index any register in the file.
7.5.1 The X-register, Y-register, and Z-register
The registers R26...R31 have some added functions to their general purpose usage.
These registers are 16-bit address pointers for indirect addressing of the data space.
The three indirect address registers X, Y, and Z are defined as described in Figure 7-2
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