參數(shù)資料
型號: IQ80C52XXX-16SHXXX:RD
廠商: TEMIC SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQFP44
文件頁數(shù): 31/60頁
文件大?。?/td> 5137K
MB89630R Series
DS07-12531-4E
37
(7) Bus Write Timing
(VCC = 5.0 V
±10%, FCH = 10 MHz, AVSS = VSS= 0.0 V, TA = –40
°C to +85°C)
*1: For information on tinst, see “(4) Instruction Cycle”.
*2: This characteristics are also applicable to the bus read timing.
Parameter
Symbol
Pin name
Condition
Value
Unit Remarks
Min.
Max.
Valid address
→ ALE ↓ time tAVLL
AD7 to AD0,
ALE
A15 to A08
1/4 tinst*1 – 64 ns*2
μs
ALE
↓ time → address loss
time
tLLAX
5—
ns
Valid address
→ WR ↓ time tAVWL
WR, ALE
1/4 tinst*1 – 60 ns*2
μs
WR pulse width
tWLWH
WR
1/2 tinst*1 – 20 ns*2
μs
Write data
→ WR ↑ time
tDVWH
AD7 to AD0, WR
1/2 tinst*1 – 60 ns*2
μs
WR
↑ → address loss time
tWHAX
WR, A15 to A08
1/4 tinst*1 – 40 ns*2
μs
WR
↑ → data hold time
tWHDX
AD7 to AD0, WR
1/4 tinst*1 – 40 ns*2
μs
WR
↑ → ALE ↑ time
tWHLH
WR, ALE
1/4 tinst*1 – 40 ns*2
μs
WR
↓ → CLK ↑ time
tWLCH
WR, CLK
1/4 tinst*1 – 40 ns*2
μs
CLK
↓ → WR ↑ time
tCLWH
0—
ns
ALE pulse width
tLHLL
ALE
1/4 tinst*1 – 35 ns*2
μs
ALE
↓ → CLK ↑ time
tLLCH
ALE,CLK
1/4 tinst*1 – 30 ns*2
μs
A15 to A08
AD7 to AD0
ALE
CLK
WR
0.8V
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
tCLWH
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
tLLAX
tLHLL
tLLCH
tAVLL
tDVWH
tWHDX
tWHAX
tWLCH
tAVWL
tWHLH
tWLWH
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