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| 型號(hào)： | IMXPWSWP_D |
| 英文描述： | i.MX Application Processor Creating Power with Stamina White Paper White Paper |
| 中文描述： | i.MX應(yīng)用處理器創(chuàng)建功耗耐力白皮書白皮書 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 217K |
| 代理商： | IMXPWSWP_D |
Creating Performance with Stamina for Wireless Communications White Paper, Rev. 2
Freescale Semiconductor
5
Motorola has a great deal of experience in wireless communications—over seventy years building wireless
products, and fifty years in the semiconductor industry. We are uniquely qualified to start with a high
performance processor core and build a high level of integration and system optimization around that core.
Doing so provides the features needed to process the latest wireless services cost effectively with low
power consumption. We learned a long time ago that low power is just as important as high performance
when designing and building portable communications devices. Because high performance usually
requires high power and low power sacrifices at least some performance, the trick is to find the perfect
balance between the two within a particular design. We optimize for performance when speed is an
absolute must and build everything else for low power. There are a number of design and manufacturing
strategies for achieving economical performance, and Motorola is adept at implementing these practices,
at system-level, chip-level, and even transistor-level designs, to achieve performance with stamina.
Dual V
T
—
Each transistor in a semiconductor design has an associated threshold voltage (V
T
) that
determines at what voltage level the gate is triggered to open or close. Typically, a lower V
T
transistor
offers higher performance because the voltage doesn’t have to swing as far to trigger the gate. However,
the manufacturing techniques necessary to produce low V
T
transistors tend to make them higher leakage
devices, so the standby current drain is higher than what you want to include in a portable, battery powered
product. In the past, we had to make a choice whether we wanted to tune a device for high speed, in which
case we would have poor standby current, or design it using higher V
T
transistors which would not run as
fast but would have less standby current drain. Now we have the ability to include both high and low V
T
transistors in the same chip, using only low V
T
transistors for those critical path circuits required to get the
speed that we want. The bulk of the device can then use the higher V
T
transistors, which have the
advantage of lower standby current.
Well-biasing
—Essentially, standby current drain is electrons “l(fā)eaking” through a gate junction of thin
oxide within the transistor. The amount of current flow is a function of the voltage across the junction. The
greater the difference between voltages on both sides of the junction, the greater the leakage—more
current is being drained, even in standby mode. By biasing up the substrate voltage to more closely match
the voltage on the other side of the transistor, the voltage across the junction is lowered, thus reducing the
leakage. This is well-biasing, and it helps reduce current drain on a transistor level whereas Dual V
T
is a
chip-level technique. Both methods can be used in a single device to minimize standby current drain.
Dynamic Voltage Frequency Scaling (DVFS)
—This is simply adjusting the clock speed and power
supply on the fly to lower current drain when full speed operation is not required. For instance, there is no
reason to run a clock at 200 MHz if the application only requires 50 MHz. Slowing the clock means the
operating voltage can be lowered, which, in turn, lessens the demand for battery power.
Dynamic Memory Access (DMA)
—This facilitates data movement with minimal processor intervention.
DMA is engineered to allow pathways between peripherals and memory to bypass the processor. It
increases efficiency and performance because of short and direct data paths, and it is designed to save the
processor from allocating power and performance to this particular task. This means the CPU can either
be used to perform other functions, which increases system performance, or, since it has less work to do,
it can be slowed down to save power.
Clock Gating
—This is an effective strategy for reducing power consumption while maintaining the same
levels of performance and functionality. Basically, a circuit uses power when it is being clocked, but leaks
a smaller amount of current (measured in micro-amps) when its clock has been gated, or tuned off. By
shutting off the clocks of unused portions of the i.MX, we have realized significant power savings during
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