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參數(shù)資料
| 型號(hào)： | IMISC627BXB |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO32 |
| 封裝： | SOIC-32 |
| 文件頁(yè)數(shù)： | 1/6頁(yè) |
| 文件大?。?/td> | 56K |
| 代理商： | IMISC627BXB |
SC627
System Clock Generator Supporting Synchronous/Asynchronous
PCI System Board Designs
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev.1.3
6/16/97
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Page 1 of 6
PRODUCT FEATURES
T Supports Synchronous / Asynchronous PCI
system board designs with P54, P55, and P6,
Cyrix and AMD CPU’s.
T 12 CPU clocks for SDRAM support.
T 90 mA buffer switching current @ 3.3V
T Current controlled buffers for lower EMI.
T Selectable Offset Delay between CPU and PCI
clocks.
T F.A.S.T. (Frequency Augmentation System Test)
function for increased host/PCI speed.
T Optional common or mixed supply mode:
VDD=VDDq=3.3V, VDD=3.3V, VDDq=2.5V.
T 32 Pin SOIC.
BLOCK DIAGRAM
FREQUENCY TABLE
Selectors
Outputs(MHz)
S2
S1
S0
CPU
PCI
F.A.S.T.
0
50
25
4.76 %
0
1
60
30
4.76 %
0
1
0
66.6
33.3
4.76 %
0
1
TEST
1
0
55
27.5
4.76 %
1
0
1
75
37.5
4.76%
1
0
75
30
4.76%
1
83.3
33.3
3.25%
CONNECTION DIAGRAM
REF
PLL1
PCI DELAY
CONTROL UNIT
PLL2
S0
S1
F.A.S.T.
REF / F.A.S.T.
48MHz
24MHz/DLY
XIN
XOUT
B
CPU(1:4), (7:11)
CPU(5:6)/S(1:2)
CPU0/S0
PCI (0:5)
12
6
DLY
S2
VDD
1
Xin
2
Xout
3
VSS
4
CPU0 / S0
5
CPU1
6
CPU2
7
VDDQ
8
CPU3
9
CPU4
10
VSS
11
CPU5 / S1
12
CPU6 / S2
13
VDDQ
14
REF / F.A.S.T.
32
48 MHZ
31
24 MHZ / DLY
30
VDD
29
PCI5
28
PCI4
27
VSS
26
PCI3
25
PCI2
24
VDD
23
PCI1
22
PCI0
21
VSS
20
CPU11
19
CPU7
15
CPU8
16
CPU10
18
CPU9
17
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