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參數(shù)資料
| 型號： | IMISC660EYB |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | LOW SKEW CLOCK DRIVER, PDSO28 |
| 封裝： | SSOP-28 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 54K |
| 代理商： | IMISC660EYB |
SC660E
I
2C System Clock Buffer for Mobile Applications
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev.2.5
2/17/2000
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Page 1 of 7
Product Features
S
10 output buffers for high clock fanout applications
S
Each output can be internally disabled for EMI and
power consumption reduction.
S
Separate power supply for each group of 2 clock
outputs for mixed voltage application.
S
< 250ps skew between output clocks.
S
28-pin SSOP package for minimum board space
S
Single output Tristate pin for testability
Block Diagram
VDDB
OE
SDATA
SDRAM(2:3)
SCLOCK
VDD
FIN
I2C
SDRAM(0:1)
SDRAM4
SDRAM5
SDRAM(8:9)
SDRAM(6:7)
Product Description
The device is a high fanout system clock distributor. Its
primary application is to create the large quantity of
clocks needed to support a wide range of clock loads
that are referenced to a single existing clock. Loads of
up to 30 pF are supported. Primary application of this
component is where long traces are used to transport
clocks from their generating devices to their loads. The
creation of EMI and the degradation of waveform rise
and fall times is greatly reduced by running a single
reference clock trace to this device and then using it to
regenerate the clock that drives shorter traces by using
the IMISC660 to generate the clocks at the target
devices EMI is therefore minimized and board real
estate is saved.
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VDDB
SDRAM9
SDRAM8
VSS
VDDB
SDRAM7
SDRAM6
VSS
OE
VDDB
SDRAM5
VSS
SCLOCK
VDDB
SDRAM0
SDRAM1
VSS
VDDB
SDRAM2
SDRAM3
VSS
FIN
VDDB
SDRAM4
VSS
VDD
SDATA
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