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39
2593O–AVR–02/12
ATmega644
8.
Power Management and Sleep Modes
8.1
Overview
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving
power. The AVR provides various sleep modes allowing the user to tailor the power consump-
tion to the application’s requirements.
8.2
Sleep Modes
bution. The figure is helpful in selecting an appropriate sleep mode.
Table 8-2 shows the
different sleep modes and their wake-up sources.
Notes:
1. Only recommended with external crystal or resonator selected as clock source.
2. If Timer/Counter2 is running in asynchronous mode.
3. For INT2:0, only level interrupt.
To enter any of the five sleep modes, the SE bit in SMCR must be written to logic one and a
SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register select
which sleep mode (Idle, ADC Noise Reduction, Power-down, Power-save, or Standby) will be
activated by the SLEEP instruction. See
Table 8-2 for a summary.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU
is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and
resumes execution from the instruction following SLEEP. The contents of the Register File and
SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode,
the MCU wakes up and executes from the Reset Vector.
Table 8-1.
Active Clock Domains and Wake-up Sources in the Different Sleep Modes.
Active Clock Domains
Oscillators
Wake-up Sources
Sleep Mode
cl
k
CPU
cl
k
FLASH
cl
k
IO
cl
k
ADC
cl
k
ASY
Mai
n
Cloc
k
So
ur
ce
Enab
led
T
imer
Osc
Enab
led
IN
T2:
0
and
Pin
Cha
n
g
e
T
W
IAd
dress
Matc
h
Ti
m
e
r2
SPM/
EEPR
O
M
R
ead
y
AD
C
WD
T
I
n
te
rr
up
t
Oth
e
rI/O
Idle
XXX
X
XXXXXXX
ADCNRM
X
XXX
Power-down
XX
Power-save
X
XX
X
XX
Extended
Standby
XX
X