參數(shù)資料
型號(hào): IDTSSTE32882KA1AKG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 63/75頁
文件大?。?/td> 0K
描述: IC REGISTERING CLK DRIVER 176BGA
標(biāo)準(zhǔn)包裝: 170
類型: 時(shí)鐘緩沖器/驅(qū)動(dòng)器,多路復(fù)用器
PLL:
主要目的: 存儲(chǔ)器,DDR3,RDIMM
輸入: CMOS
輸出: CMOS
電路數(shù): 1
比率 - 輸入:輸出: 5:60
差分 - 輸入:輸出: 是/是
頻率 - 最大: 810MHz
電源電壓: 1.282 V ~ 1.575 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 176-TFBGA
供應(yīng)商設(shè)備封裝: 176-CABGA(13.5x8)
包裝: 托盤
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
66
SSTE32882KA1
7314/8
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
Test Circuits and Switching Waveforms
Parameter Measurement Information
All input pulses are supplied by generators having the following characteristics: 300MHz
≤ PRR ≤ 945 MHz; Zo = 50 Ω; input
slew rate = 1 V/ns ± 20%, unless otherwise specified. The outputs are measured one at a time with one transition per
measurement.
Qn and Yn Load circuit for propagation delay and slew measurement
1 CL is parasitic (probe and jig capacitance).
Voltage waveforms; propagation delay times
VTT = VDD/2
VICR Cross Point Voltage
VI(P-P) = 500mV (1.5V operation), 450mV (1.35V operation) or 400mv (1.25V operation).
tPDM1, tPDM2 the larger number of both has to be taken when performing tPDM max measurement, the smaller number of both
has to be taken when performing tPDM min measurement.
CL<2.5pF(1)
DUT
OUT
Test point
CK Inputs
TL = 50
Ω
RL = 100
Ω
Test point
VTT
RL=50
Ω
CK
Trace delay matched on load board
VTT
Q Output
VTT
CK
tPDM1tPDM2
VICR
VI(P-P)
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