Figure-23 JTAG State Diagram Pause-IR The paus" />
參數(shù)資料
型號： IDT82V2088BBG
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 57/78頁
文件大?。?/td> 0K
描述： IC LINE INTERFACE UNIT 208-PBGA
標(biāo)準(zhǔn)包裝： 10
類型： 線路接口裝置（LIU）
規(guī)程： E1
電源電壓： 3.13 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 208-BGA
供應(yīng)商設(shè)備封裝： 208-PBGA（17x17）
包裝： 托盤
其它名稱： 800-1705
82V2088BBG
60
INDUSTRIAL
TEMPERATURE RANGES
OCTAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
Figure-23 JTAG State Diagram
Pause-IR
The pause state allows the test controller to temporarily halt the shifting of data through the instruction register. The test data register
selected by the current instruction retains its previous value and the instruction does not change during this state. The controller remains in
this state as long as TMS is low. When TMS goes high and a rising edge is applied to TCK, the controller moves to the Exit2-IR state.
Exit2-IR
This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-IR
state, which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Shift-IR state.
The test data register selected by the current instruction retains its previous value and the instruction does not change during this state.
Update-IR
The instruction shifted into the instruction register is latched into the parallel output from the shift-register path on the falling edge of TCK.
When the new instruction has been latched, it becomes the current instruction. The test data registers selected by the current instruction
retain their previous value.
Table-59 TAP Controller State Description (Continued)
STATE
DESCRIPTION
Test-logic Reset
Run Test/Idle
Select-DR
Select-IR
Capture-DR
Capture-IR
Shift-DR
Shift-IR
Exit1-DR
Exit1-IR
Pause-DR
Pause-IR
Exit2-DR
Exit2-IR
Update-DR
Update-IR
1
0
1
00
0
1
0
1
0
1
0
1
0
1
0
1
0
1
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