參數(shù)資料
型號(hào): IDT72615L50PF
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 1/17頁(yè)
文件大?。?/td> 0K
描述: IC FIFO BY SYNC 512X18X2 64QFP
標(biāo)準(zhǔn)包裝: 90
系列: 7200
功能: 同步
存儲(chǔ)容量: 18.4K(512 x 18 x 2)
訪問(wèn)時(shí)間: 50ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(14x14)
包裝: 托盤(pán)
其它名稱(chēng): 72615L50PF
CMOS SyncBiFIFOTM
256 x 18 x 2
512 x 18 x 2
IDT72605
IDT72615
1
2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-2704/10
FEBRUARY 2013
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
FUNCTIONAL BLOCK DIAGRAM
FEATURES:
Two independent FIFO memories for fully bidirectional data
transfers
256 x 18 x 2 organization (IDT72605)
512 x 18 x 2 organization (IDT72615)
Synchronous interface for fast (20ns) read and write cycle times
Each data port has an independent clock and read/write control
Output enable is provided on each port as a three-state control
of the data bus
Built-in bypass path for direct data transfer between two ports
Two fixed flags, Empty and Full, for both the A-to-B and the B-
to-A FIFO
Programmable flag offset can be set to any depth in the FIFO
The synchronous BiFIFO is packaged in a 64-pin TQFP (Thin
Quad Flatpack) and 68-pin PLCC
Industrial temperature range (–40
°°°°°C to +85°°°°°C)
Green parts available, see ordering information
DESCRIPTION:
The IDT72605 and IDT72615 are very high-speed, low-power bidirec-
tionalFirst-In,First-Out(FIFO)memories,withsynchronousinterfaceforfast
read and write cycle times. The SyncBiFIFO is a data buffer that can store
orretrieveinformationfromtwosourcessimultaneously.TwoDual-PortFIFO
memory arrays are contained in the SyncBiFIFO; one data buffer for each
direction.
The SyncBiFIFO has registers on all inputs and outputs. Data is only
transferred into the I/O registers on clock edges, hence the interfaces are
synchronous. EachPorthasitsownindependentclock.Datatransferstothe
I/O registers are gated by the enable signals. The transfer direction for each
portiscontrolledindependentlybyaread/writesignal. Individualoutputenable
signals control whether the SyncBiFIFO is driving the data lines of a port or
whether those data lines are in a high-impedance state.
Bypass control allows data to be directly transferred from input to output
registerineitherdirection.
TheSyncBiFIFOhaseightflags.TheflagpinsareFull,Empty,Almost-Full,
andAlmost-EmptyforbothFIFOmemories.TheoffsetdepthsoftheAlmost-Full
andAlmost-Emptyflagscanbeprogrammedtoanylocation.
TheSyncBiFIFOisfabricatedusinghigh-speed,submicronCMOStech-
nology.
CLKA
FLAG
LOGIC
MEMORY
ARRAY
512 x 18
256 x 18
INPUT REGISTER
MUX
OUTPUT REGISTER
HIGH
Z
CONTROL
OUTPUT REGISTER
INPUT REGISTER
CLKB
MUX
MEMORY
ARRAY
512 x 18
256 x 18
HIGH
Z
CONTROL
FLAG
LOGIC
RESET
LOGIC
POWER
SUPPLY
R/
WA
CSA
A2
A1
A0
EFAB
PAEAB
PAFAB
FFAB
OEB
R/
WB
ENB
ENA
OEA
RS
EFBA
PAEBA
PAFBA
FFBA
VCC
GND
3
BYPB
μP
INTERFACE
7
DB0-DB17
DA0-DA17
2704 drw 01
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