參數(shù)資料
型號: IDT82V2082BFG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 3/88頁
文件大?。?/td> 0K
描述: IC LIU T1/E1/J1 2CH 81BGA
標準包裝: 360
類型: 線路接口裝置(LIU)
規(guī)程: T1,E1,J1
電源電壓: 3.13 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 81-LFBGA
供應商設備封裝: 81-CABGA(8x8)
包裝: 托盤
IDT82V2082
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
PIN DESCRIPTION
11
May 4, 2009
Notes:
1. The footprint ‘n’ (n = 1~2) represents one of the two channels.
2. The name and address of the registers that contain the preceding bit. Only the address of channel 1 register is listed, the rest addresses are represented by ‘...’. Users can find
these omitted addresses in the Register Description section.
3. TCLKn missing: the state of TCLKn continues to be high level or low level over 70 MCLK cycles.
2
PIN DESCRIPTION
Table-1 Pin Description
Name
Type
TQFP80
Pin No.
FPBGA81
Pin No.
Description
TTIP1
TTIP2
TRING1
TRING2
Analog
Output
63
78
62
79
A7
A3
A8
A2
TTIPn1/TRINGn: Transmit Bipolar Tip/Ring for Channel 1~2
These pins are the differential line driver outputs and can be set to high impedance state globally or individually. A logic
high on THZ pin turns all these pins into high impedance state. When THZ bit (TCF1, 03H...)2 is set to ‘1’, the TTIPn/
TRINGn in the corresponding channel is set to high impedance state.
In summary, these pins will become high impedance in the following conditions:
THZ pin is high: all TTIPn/TRINGn enter high impedance;
THZn bit is set to 1: the corresponding TTIPn/TRINGn become high impedance;
Loss of MCLK: all TTIPn/TRINGn pins become high impedance;
Loss of TCLKn: the corresponding TTIPn/TRINGn become HZ (exceptions: Remote Loopback; Transmit internal
pattern by MCLK);
Transmitter path power down: the corresponding TTIPn/TRINGn become high impedance;
After software reset; pin reset and power on: all TTIPn/TRINGn enter high impedance.
RTIP1
RTIP2
RRING1
RRING2
Analog
Input
67
74
66
75
E5
D5
D6
C4
RTIPn/RRINGn: Receive Bipolar Tip/Ring for Channel 1~2
These signals are the differential receiver inputs.
TD1/TDP1
TD2/TDP2
TDN1
TDN2
I37
23
36
24
H7
H3
G6
H2
TDn: Transmit Data for Channel 1~2
When the device is in single rail mode, the NRZ data to be transmitted is input on this pin. Data on TDn pin is sampled
into the device on the active edge of TCLKn and is encoded by AMI, HDB3 or B8ZS line code rules before being trans-
mitted. In this mode, TDNn should be connected to ground.
TDPn/TDNn: Positive/Negative Transmit Data
When the device is in dual rail mode, the NRZ data to be transmitted for positive/negative pulse is input on these pins.
Data on TDPn/TDNn pin is sampled into the device on the active edge of TCLKn. The active polarity is also selectable.
Refer to 3.3.1 TRANSMIT PATH SYSTEM INTERFACE for details. The line code in dual rail mode is as follows:
TCLK1
TCLK2
I38
22
J7
J3
TCLKn: Transmit Clock for Channel 1~2
This pin inputs 1.544 MHz for T1/J1 mode or 2.048 MHz for E1 mode transmit clock. The transmit data at TDn/TDPn or
TDNn is sampled into the device on the active edge of TCLKn. If TCLKn is missing3 and the TCLKn missing interrupt is
not masked, an interrupt will be generated.
TDPn
TDNn
Output Pulse
0
Space
0
1
Positive Pulse
1
0
Negative Pulse
1
Space
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