參數(shù)資料
型號： IDT82V2052EPFG
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 9/70頁
文件大?。?/td> 0K
描述： IC LIU E1 2CH SHORT HAUL 80-TQFP
標(biāo)準(zhǔn)包裝： 45
類型： 線路接口裝置（LIU）
規(guī)程： E1
電源電壓： 3.13 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-TQFP（14x14）
包裝： 托盤
其它名稱： 82V2052EPFG
IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION
17
December 12, 2005
3
FUNCTIONAL DESCRIPTION
3.1
CONTROL MODE SELECTION
The IDT82V2052E can be configured by software or by hardware. The
softwarecontrolmodesupportsSerialControlInterface,Motorolanon-Mul-
tiplexed Control Interface and Intel non-Multiplexed Control Interface. The
Control mode is selected by MODE1 and MODE0 pins as follows:
The serial microcontroller Interface consists of CS, SCLK, SCLKE,
SDI, SDO and INT pins. SCLKE is used for the selection of active
edge of SCLK.
The parallel non-Multiplexed microcontroller Interface consists of
CS, A[5:0], D[7:0], DS/RD, R/W/WR and INT pins.
Hardware interface consists of PULSn, THZ, RCLKE, LPn[1:0],
PATTn[1:0], JA[1:0], MONTn, TERMn, RPDn, MODE[1:0] and
RXTXM[1:0] (n=1, 2). Refer to 5 HARDWARE CONTROL PIN SUM-
for details about hardware control.
3.2
TRANSMIT PATH
The transmit path of each channel of IDT82V2052E consists of an
Encoder, an optional Jitter Attenuator, a Waveform Shaper, a Line Driver
and a Programmable Transmit Termination.
3.2.1
TRANSMIT PATH SYSTEM INTERFACE
The transmit path system interface consists of TCLKn pin, TDn/TDPn
pinandTDNnpin.TCLKnisa2.048MHzclock.IfTCLKnismissingformore
than 70 MCLK cycles, an interrupt will be generated if it is not masked.
Transmit data is sampled on theTDn/TDPnand TDNnpins bythe active
edge of TCLKn. The active edge of TCLKn can be selected by the
TCLK_SELbit(TCF0,04H...).AndtheactivelevelofthedataonTDn/TDPn
and TDNn can be selected by the TD_INV bit (TCF0, 04H...). In hardware
control mode, the falling edge of TCLKn and the active high of transmit data
are always used.
The transmit data from the system side can be provided in two different
ways: Single Rail and Dual Rail. In Single Rail mode, only TDn pin is used
for transmitting data and the T_MD[1] bit (TCF0, 04H...) should be set to
‘0’.InDualRailMode,bothTDPnpinandTDNnpinareusedfortransmitting
data, the T_MD[1] bit (TCF0, 04H...) should be set to ‘1’.
3.2.2
ENCODER
In Single Rail mode, the Encoder can be configured to be a HDB3
encoder or an AMI encoder by setting T_MD[0] bit (TCF0, 04H...).
In Dual Rail mode, the Encoder is by-passed. In Dual Rail mode, a logic
‘1’ontheTDPn pinanda logic‘0’ ontheTDNnpin resultsin anegative pulse
on the TTIPn/TRINGn; a logic ‘0’ on TDPn pin and a logic ‘1’ on TDNn pin
results in a positive pulse on the TTIPn/TRINGn. If both TDPn and TDNn
are high or low, the TTIPn/TRINGn outputs a space (Refer to TDn/TDPn,
In hardware control mode, the operation mode of receive and transmit
path can be selected by setting RXTXM1 and RXTXM0 pins on a global
basis. Refer to 5 HARDWARE CONTROL PIN SUMMARY for details.
3.2.3
PULSE SHAPER
The IDT82V2052E provides two ways of manipulating the pulse shape
before sending it. One is to use preset pulse templates; the other is to use
user-programmable arbitrary waveform template.
In software control mode, the pulse shape can be selected by setting
the related registers.
In hardware control mode, the pulse shape can be selected by setting
PULSn pins on a per channel basis. Refer to 5 HARDWARE CONTROL PIN
for details.
3.2.3.1 Preset Pulse Templates
The pulse shape is shown in Figure-3 according to the G.703 and the
measuring diagram is shown in Figure-4. In internal impedance matching
mode, if the cable impedance is 75
, the PULS[3:0] bits (TCF1, 05H...)
should be set to ‘0000’; if the cable impedance is 120
, the PULS[3:0] bits
(TCF1, 05H...) should be set to ‘0001’. In external impedance matching
mode, for both E1/75
andE1/120cableimpedance,PULS[3:0]should
be set to ‘0001’.
Figure-3 E1 Waveform Template Diagram
Control Interface Mode
00
Hardware interface
01
Serial Microcontroller Interface.
10
Parallel -non-Multiplexed -Motorola Interface
11
Parallel -non-Multiplexed -Intel Interface
-0 .6
-0 .4
-0 .2
0
0 .2
0 .4
0.6
-0 .2 0
0.00
0.2 0
0.4 0
0.6 0
0.8 0
1.00
1.2 0
T im e in U n it In te rv a ls
N
orm
al
iz
ed
A
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pl
itud
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