參數(shù)資料
型號： IDT82V2052EPFG
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 32/70頁
文件大?。?/td> 0K
描述： IC LIU E1 2CH SHORT HAUL 80-TQFP
標準包裝： 45
類型： 線路接口裝置（LIU）
規(guī)程： E1
電源電壓： 3.13 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 80-LQFP
供應商設備封裝： 80-TQFP（14x14）
包裝： 托盤
其它名稱： 82V2052EPFG
IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
PROGRAMMING INFORMATION
38
December 12, 2005
4.3
REGISTER DESCRIPTION
4.3.1
GLOBAL REGISTERS
Table-15 ID: Device Revision Register
(R, Address = 00H)
Symbol
Bit
Default
Description
ID[7:0]
7-0
00H
Current Silicon Chip ID.
Table-16 RST: Reset Register
(W, Address = 01H)
Symbol
Bit
Default
Description
RST[7:0]
7-0
00H
Software reset. A write operation on this register will reset all internal registers to their default values, and the status
of all ports are set to the default status. The content in this register can not be changed. After reset, all drivers output
are in high impedance state.
Table-17 GCF: Global Configuration Register
(R/W, Address = 20H)
Symbol
Bit
Default
Description
MONT[1:0]
7-6
00
G.772 monitor
= 00/10: Normal
= 01: Receiver 1 monitors the receive path of channel 2
= 11: Receiver 1 monitors the transmit path of channel 2
-
5-4
00
Reserved.
COPY
3
0
Enable broadcasting mode.
= 0: Broadcasting mode disabled
= 1: Broadcasting mode enabled. Writing operation on one channel's register will be copied exactly to the corre-
sponding registers in other channel.
INTM_GLB
2
1
Global interrupt enable
= 0: Interrupt is globally enabled. But for each individual interrupt, it still can be disabled by its corresponding Inter-
rupt mask Bit.
= 1: All the interrupts are disabled for both channels.
INT_PIN[1:0]
1-0
00
Interrupt pin control
= x0: Open drain, active low (with an external pull-up resistor)
= 01: Push-pull, active low
= 11: Push-pull, active high
Table-18 INTCH: Interrupt Channel Indication Register
(R, Address =21H)
Symbol
Bit
Default
Description
-
7-2
000000
Reserved.
INT_CH[1:0]
1-0
00
INT_CH[n]=0 indicates that an interrupt was generated by channel [n+1].
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