參數(shù)資料
型號： IDT82V2048SDAG
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 11/62頁
文件大?。?/td> 0K
描述： IC LIU T1/E1 8CH SHORT 144-TQFP
標(biāo)準(zhǔn)包裝： 5,000
類型： 線路接口裝置（LIU）
規(guī)程： E1
電源電壓： 3.13 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-TQFP（20x20）
包裝： 托盤
其它名稱： 82V2048SDAG
19
IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION
INDUSTRIAL TEMPERATURE RANGES
2.5.2
BIPOLAR VIOLATION INSERTION
When configured in Single Rail Mode 2 with AMI line code enabled,
pin TDNn/BPVIn is used as BPVI input. A low-to-high transition on this
pin inserts a bipolar violation on the next available mark in the transmit
data stream. Sampling occurs on the falling edges of TCLK. But in TAOS
(Transmit All Ones) with Analog Loopback, Remote Loopback and
Inband Loopback, the BPVI is disabled. In TAOS with Digital Loopback,
the BPVI is looped back to the system side, so the data to be transmitted
on TTIPn and TRINGn are all ones with no bipolar violation.
2.6
JITTER ATTENUATOR
The jitter attenuator can be selected to work either in transmit path or
in receive path or not used. The selection is accomplished by setting pin
JAS in hardware mode or configuring bits JACF[1:0] in register GCF in
host mode, which affects all eight channels.
For applications which require line synchronization, the line clock
needed to be extracted for the internal synchronization, the jitter attenu-
ator is set in the receive path. Another use of the jitter attenuator is to
provide clock smoothing in the transmit path for applications such as
synchronous/asynchronous demultiplexing applications. In these appli-
cations, TCLK will have an instantaneous frequency that is higher than
the nominal T1/E1 data rate and in order to set the average long-term
TCLK frequency within the transmit line rate specifications, periods of
TCLK are suppressed (gapped).
The jitter attenuator integrates a FIFO which can accommodate a
gapped TCLK. In host mode, the FIFO length can be 32 X 2 or 64 X 2
bits by programming bit JADP in GCF. In hardware mode, it is fixed to 64
X 2 bits. The FIFO length determines the maximum permissible gap
width (see Table-10 Gap Width Limitation). Exceeding these values will
cause FIFO overflow or underflow. The data is 16 or 32 bits’ delay
through the jitter attenuator in the corresponding transmit or receive
path. The constant delay feature is crucial for the applications requiring
“hitless” switching.
In host mode, bit JABW in GCF determines the jitter attenuator 3 dB
corner frequency (fc) for both T1 and E1. In hardware mode, the fc is
fixed to 2.5 Hz for T1 or 1.7 Hz for E1. Generally, the lower the fc is, the
higher the attenuation. However, lower fc comes at the expense of
increased acquisition time. Therefore, the optimum fc is to optimize both
the attenuation and the acquisition time. In addition, the longer FIFO
length results in an increased throughput delay and also influences the 3
dB corner frequency. Generally, it’s recommended to use the lower
corner frequency and the shortest FIFO length that can still meet jitter
attenuation requirements.
2.7
LINE INTERFACE CIRCUITRY
The transmit and receive interface RTIPn/RRINGn and TTIPn/
TRINGn connections provide a matched interface to the cable. Figure-
12 and Figure-13 show the appropriate external components to connect
with the cable for one transmit/receive channel. Table-12 summarizes
the component values based on the specific application.
Table-9 Built-in Waveform Template Selection
TS2
TS1
TS0
Service
Clock Rate
Cable Length
Maximum Cable Loss (dB)(1)
1. Maximum cable loss at 772 kHz.
0
E1
2.048 MHz
120
/75 Cable
-
00
1
Reserved
01
0
01
1
T1
1.544 MHz
0-133 ft. ABAM
0.6
1
0
133-266 ft. ABAM
1.2
1
0
1
266-399 ft. ABAM
1.8
1
0
399-533 ft. ABAM
2.4
1
533-655 ft. ABAM
3.0
Table-10 Gap Width Limitation
FIFO Length
Max. Gap Width
64 bit
56 UI
32 bit
28 UI
Table-11 Output Jitter Specification
T1
E1
AT&T Pub 62411
ITU-T G.736
GR-253-CODE
ITU-T G.742
TR-TSY-000009
ITU-T G.783
ETSI CTR 12/13
Table-12 External Components Values
Component
E1
T1
75
Coax
120
Twisted Pair
100
Twisted Pair, VDDT = 5.0 V
R
T
9.5
± 1%
9.5
± 1%
9.1
± 1%
R
9.31
± 1%
15
± 1%
12.4
± 1%
Cp
2200 pF
1000 pF
D1 - D4
Nihon Inter Electronics - EP05Q03L, 11EQS03L, EC10QS04, EC10QS03L; Motorola - MBR0540T1
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