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參數(shù)資料
| 型號： | IDT82V2048SDAG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 10/62頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/E1 8CH SHORT 144-TQFP |
| 標準包裝： | 5,000 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | E1 |
| 電源電壓： | 3.13 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-TQFP（20x20） |
| 包裝： | 托盤 |
| 其它名稱： | 82V2048SDAG |
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18
IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION
INDUSTRIAL TEMPERATURE RANGES
Figure-9 B8ZS Excessive Zeros
2.5
TRANSMITTER
In transmit path, data in NRZ format are clocked into the device on
TDn and encoded by AMI or B8ZS/HDB3 line code rules when single rail
mode is configured or pre-encoded data in NRZ format are input on
TDPn and TDNn when dual rail mode is configured. The data are
sampled into the device on falling edges of TCLKn. Jitter attenuator, if
enabled, is provided with a FIFO through which the data to be trans-
mitted are passing. A low jitter clock is generated by an integral digital
phase-locked loop and is used to read data from the FIFO. The shape of
the pulses are user programmable to ensure that the T1/E1 pulse
template is met after the signal passes through different cable lengths or
types. Bipolar violation, for diagnosis, can be inserted on pin BPVIn if
AMI line code rule is enabled.
2.5.1
WAVEFORM SHAPER
T1 pulse template, specified in the DSX-1 Cross-Connect by ANSI
T1.102, is illustrated in Figure-10. The device has built-in transmit wave-
form templates, corresponding to 5 levels of pre-equalization for cable of
a length from 0 ft to 655 ft with each increment of 133 ft.
E1 pulse template, specified in ITU-T G.703, is shown in Figure-11.
The device has built-in transmit waveform templates for cable of 75 or
120 .
Any one of the six built-in waveforms can be chosen in both hard-
ware mode and host mode. In hardware mode, setting pins TS[2:0] can
select the required waveform template for all the transmitters, as shown
in Table-9. In host mode, the waveform template can be configured on a
per-channel basis. Bits TSIA[2:0] in register TSIA are used to select the
channel and bits TS[2:0] in register TS are used to select the required
waveform template.
The built-in waveform shaper uses an internal high frequency clock
which is 16XMCLK as the clock reference. This function will be
bypassed when MCLK is unavailable.
Figure-10 DSX-1 Waveform Template
Figure-11 CEPT Waveform Template
Excessive zeros detected
RCLKn
RTIPn
RRINGn
RDn
CVn
8 consecutive zeros
12
3
1
45
6
7
8
2
35
46
7
8
9
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
1.2
0
250
500
750
1000
1250
Time (ns)
Normalized
Amplit
ude
-300
-200
-100
0
100
200
300
Time (ns)
-0.20
0.00
0.20
0.40
0.60
0.80
1.00
1.20
Nor
m
al
iz
ed
A
m
pli
tude
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| IDT82V2051EPP | 功能描述:IC LIU E1 SGL SHORT HAUL 44-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標準包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82V2051EPP8 | 功能描述:IC LIU E1 SGL SHORT HAUL 44-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標準包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82V2051EPPG | 功能描述:IC LIU E1 SGL SHORT HAUL 44-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標準包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
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