參數(shù)資料
型號: IDT82V2048LBBG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 45/48頁
文件大小: 0K
描述: IC LIU T1/E1 8CH SHORT 160-BGA
標(biāo)準包裝: 14
類型: 線路接口裝置(LIU)
規(guī)程: E1
電源電壓: 3.13 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 160-BGA
供應(yīng)商設(shè)備封裝: 160-PBGA(15x15)
包裝: 托盤
其它名稱: 82V2048LBBG
6
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
MCLK
I
10
E1
MCLK: Master Clock
This is an independent, free running reference clock. A clock of 1.544 MHz (for T1 mode) or 2.048 MHz
(for E1 mode) is supplied to this pin as the clock reference of the device for normal operation.
When MCLK is low, all the receivers are powered down, and the output pins RCn, RDPn and RDNn are
switched to high impedance.
In transmit path, the operation mode is decided by the combination of MCLK and TCLKn (See Table-2
NOTE: Wait state generation via RDY/ACK is not available if MCLK is not provided.
LOS0
LOS1
LOS2
LOS3
LOS4
LOS5
LOS6
LOS7
O
42
35
75
68
113
106
3
140
K4
K3
K12
K11
E11
E12
E3
E4
LOSn: Loss of Signal Output for Channel 0~7
A high level on this pin indicates the loss of signal when there is no transition over a specified period of
time or no enough ones density in the received signal. The transition will return to low automatically when
there is enough transitions over a specified period of time with a certain ones density in the received sig-
nal. The LOS assertion and desertion criteria are described in 2.4.3 Loss of Signal (LOS) Detection.
Hardware/Host Control Interface
MODE2
I
(Pulled to
VDDIO/2)
11
E2
MODE2: Control Mode Select 2(2)
The signal on this pin determines which control mode is selected to control the device:
Hardware control pins include MODE[2:0], TS[2:0], CLKE and OE.
Serial host Interface pins include CS, SCLK, SDI, SDO and INT.
Parallel host Interface pins include CS, A[4:0], D[7:0], WR/DS, RD/R/W, ALE/AS, INT and RDY/ACK. The
device supports multiple parallel host interface as follows (refer to MODE1 and MODE0 pin descriptions
below for details):
MODE1
I
43
K2
MODE1: Control Mode Select 1(2)
In parallel host mode, the parallel interface operates with separate address bus and data bus when this pin
is low, and operates with multiplexed address and data bus when this pin is high.
In serial host mode or hardware mode, this pin should be grounded.
MODE0
I
88
H12
MODE0: Control Mode Select 0(2)
In parallel host mode, the parallel host interface is configured for Motorola compatible hosts when this pin
is low, or for Intel compatible hosts when this pin is high.
In serial host mode or hardware mode, this pin should be grounded.
CS
I
(Pulled to
VDDIO/2)
87
J11
CS: Chip Select (Active Low)
In host mode, this pin is asserted low by the host to enable host interface. A high to low transition must
occur on this pin for each read/write operation and the level must not return to high until the operation is
over.
In hardware control mode, this pin should be pulled to VDDIO/2.
Table-1 Pin Description (Continued)
Name
Type
Pin No.
Description
TQFP144 PBGA160
MODE2
Control Interface
Low
Hardware Mode
VDDIO/2
Serial Host Interface
High
Parallel Host Interface
MODE[2:0]
Host Interface
100
Non-multiplexed Motorola Mode Interface
101
Non-multiplexed Intel Mode Interface
110
Multiplexed Motorola Mode Interface
111
Multiplexed Intel Mode Interface
2. In host mode, register e-AFE has to be set to ‘FFH’ for proper device operation. See Expanded Register Description on page 28 for more details.
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