參數(shù)資料
型號: IDT82P2521BHG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 128/147頁
文件大?。?/td> 0K
描述: IC LIU E1 21+1CH SHORT 640-PBGA
標(biāo)準(zhǔn)包裝: 5
類型: 線路接口裝置(LIU)
規(guī)程: E1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 640-BGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 640-PBGA-EP(31x31)
包裝: 托盤
其它名稱: 82P2521BHG
IDT82P2521
21(+1) CHANNEL HIGH-DENSITY E1 LINE INTERFACE UNIT
Programming Information
81
December 7, 2005
REFCF - REFA/B Output Configuration Register
Address: 200H
Type: Read / Write
Default Value: 30H
Bit
Name
Description
7-
Reserved.
6
JA_BYPAS
This bit is valid only when the clock source for REFA or REFB is the recovered clock of one of the 22 channels in the correspond-
ing receiver. This bit determines whether the selected recovered clock passes through the RJA.
0: The selected recovered clock is derived from the output of RJA. (default)
1: The selected recovered clock does not pass through the RJA and is derived from the output of Rx Clock & Data Recovery.
5
REFH
This bit is valid only when the selected clock source is lost. This bit controls the output on REFA/REFB.
For REFA, this bit, together with the FS_BYPAS bit (b4, REFCF) and the FREE bit (b3, REFCF), controls the output on REFA
when the selected clock source is the recovered clock of one of the 22 channels; this bit is ignored when the selected clock
source is CLKA. Refer to the related table in the description of the FREE bit (b3, REFCF).
For REFB:
0: Output free running clock. The frequency is 2.048 MHz.
1: Output high level. (default)
4
FS_BYPAS
This bit determines whether the selected clock source for REFA passes through an internal Frequency Synthesizer.
0: The internal Frequency Synthesizer is enabled.
1: The internal Frequency Synthesizer is bypassed. (default)
3
FREE
This bit is valid only when the selected clock source for REFA passes the internal Frequency Synthesizer
In normal operation:
0: Output the clock which is locked to the selected clock source and the frequency is programmed in the FREQ[2:0] bits (b2~0,
REFCF). (default)
1: Output free running clock which is locked to MCLK and the frequency is programmed in the FREQ[2:0] bits (b2~0, REFCF).
When the selected clock source is lost, this bit, together with the FS_BYPAS bit (b4, REFCF) and the REFH bit (b5, REFCF),
controls the output on REFA:
7654321
0
-
JA_BYPAS
REFH
FS_BYPAS
FREE
FREQ2
FREQ1
FREQ0
Selected Clock
Source
FS_BYPA
S
FREE
REFH
Output On REFA
CLKA
0
(don’t-
care)
High level.
1
Free running clock, whose frequency is programmed
in the FREQ[2:0] bits (b2~0, REFCF).
1
(don’t-care)
High level.
Recovered clock of
one of the 22 chan-
nels.
0
Free running clock, whose frequency is programmed
in the FREQ[2:0] bits (b2~0, REFCF).
1
High level.
1
(don’t-
care)
Free running clock, whose frequency is programmed
in the FREQ[2:0] bits (b2~0, REFCF).
1
(don’t-
care)
0
Free running clock, whose frequency is 2.048 MHz.
1
High level.
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