- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1924 > IDT82P20416DBFG (IDT, Integrated Device Technology Inc)IC LIU T1/E1/J1 16CH SH 484BGA PDF資料下載
參數(shù)資料
| 型號： | IDT82P20416DBFG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 31/121頁 |
| 文件大小： | 0K |
| 描述： | IC LIU T1/E1/J1 16CH SH 484BGA |
| 標準包裝： | 84 |
| 功能： | 線路接口單元（LIU） |
| 接口： | E1，J1，T1 |
| 電路數(shù)： | 16 |
| 電源電壓： | 1.8V, 3.3V |
| 功率（瓦特）： | 3.10W |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 484-LFBGA |
| 供應(yīng)商設(shè)備封裝： | 484-CABGA（19x19） |
| 包裝： | 托盤 |
| 包括： | AIS 警報檢測器和發(fā)生器，回送功能，PRBS 發(fā)生器 / 檢測器，遠程檢測器和發(fā)生器 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當前第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁
IDT82P20416
16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Pin Description
17
December 17, 2009
GPIO[0]
GPIO[1]
Output / Input
V10
AA10
GPIO: General Purpose I/O [1:0]
These two pins can be defined as input pins or output pins by the DIR[1:0] bits (b1~0, GPIO)
respectively.
When the pins are input, their polarities are indicated by the LEVEL[1:0] bits (b3~2, GPIO)
respectively.
When the pins are output, their polarities are controlled by the LEVEL[1:0] bits (b3~2, GPIO)
respectively.
RST
Input
AA11
RST: Reset (Active Low)
A low pulse on this pin resets the device. This hardware reset process completes in 2 s max-
imum. Refer to Section 4.1 Reset for an overview on reset options.
MCU Interface
INT
Output
AB13
INT: Interrupt Request
This pin indicates interrupt requests for all unmasked interrupt sources.
The output characteristics (open drain or push-pull internally) and the active level are deter-
mined by the INT_PIN[1:0] bits (b3~2, GCF).
CS
Input
V13
CS: Chip Select (Active Low)
This pin must be asserted low to enable the microprocessor interface.
A transition from high to low must occur on this pin for each Read/Write operation and CS
should remain low until the operation is over.
SCLK
Input
AB12
SCLK: Shift Clock
In Serial microprocessor interface, this multiplex pin is used as SCLK.
SCLK inputs the shift clock for the Serial microprocessor interface. Data on SDI is sampled by
the device on the rising edge of SCLK. Data on SDO is updated on the falling edge of SCLK.
SDI
Input
W13
SDI: Serial Data Input
In Serial microprocessor interface, this multiplex pin is used as SDI.
Address and data on this pin are serially clocked into the device on the rising edge of SCLK.
SDO
Output
AA12
SDO: Serial Data Output
In Serial microprocessor interface, this multiplex pin is used as SDO.
Data on this pin is serially clocked out of the device on the falling edge of SCLK.
JTAG (per IEEE 1149.1)
TRST
Input
Pull-Down
AB8
TRST: JTAG Test Reset (Active Low)
A low signal on this pin resets the JTAG test port. To ensure deterministic operation of the test
logic, TMS should be held high when the signal on TRST changes from low to high.
This pin may be left unconnected when JTAG is not used.
This pin has an internal pull-down resistor.
TMS
Input
Pull-up
W11
TMS: JTAG Test Mode Select
The signal on this pin controls the JTAG test performance and is sampled on the rising edge
of TCK. To ensure deterministic operation of the test logic, TMS should be held high when the
signal on TRST changes from low to high.
This pin may be left unconnected when JTAG is not used.
This pin has an internal pull-up resistor.
TCK
Input
W12
TCK: JTAG Test Clock
The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge
of TCK and TDO is updated on the falling edge of TCK.
When TCK is idle at low state, all stored-state devices contained in the test logic shall retain
their state indefinitely.
This pin should be connected to GNDD when JTAG is not used.
Name
I / O
Pin No.
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT82P20516DBFG | IC LIU T1/E1/J1 16CH SH 484BGA |
| IDT82P2281PF | TXRX T1/E1/J1 LONG/SHORT 80-TQFP |
| IDT82P2282PF | TXRX T1/J1/E1 2CHAN 100-TQFP |
| IDT82P2284BB | TXRX T1/J1/E1 4CHAN 208-PBGA |
| IDT82P2288BBG | TXRX OCTAL T1/E1/J1 256-PBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT82P20416DBFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC LIU T1/E1/J1 16CH SH 484BGA |
| IDT82P20416DBFGBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:16-Channel Short Haul T1/E1/J1 Line Interface Unit |
| IDT82P20516 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:16-Channel Short Haul E1 Line Interface Unit |
| IDT82P20516BFBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:16-Channel Short Haul E1 Line Interface Unit |
| IDT82P20516BFGBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:16-Channel Short Haul E1 Line Interface Unit |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。