參數(shù)資料
型號: IDT79RC32H435-400BC
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 1/53頁
文件大?。?/td> 0K
描述: IC MPU 32BIT CORE 400MHZ 256-BGA
標準包裝: 90
系列: Interprise™
處理器類型: MIPS32 32-位
速度: 400MHz
電壓: 1.2V
安裝類型: 表面貼裝
封裝/外殼: 256-LBGA
供應(yīng)商設(shè)備封裝: 256-CABGA(17x17)
包裝: 托盤
其它名稱: 79RC32H435-400BC
1 of 53
January 19, 2006
2005 Integrated Device Technology, Inc.
DSC 6214
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
Device Overview
The 79RC32435 is a member of the IDT Interprise family of PCI
integrated communications processors. It incorporates a high perfor-
mance CPU core and a number of on-chip peripherals. The integrated
processor is designed to transfer information from I/O modules to main
memory with minimal CPU intervention, using a highly sophisticated
direct memory access (DMA) engine. All data transfers through the
RC32435 are achieved by writing data from an on-chip I/O peripheral to
main memory and then out to another I/O module.
Features
x
32-bit CPU Core
– MIPS32 instruction set
– Cache Sizes: 8KB instruction and data caches, 4-Way set
associative, cache line locking, non-blocking prefetches
– 16 dual-entry JTLB with variable page sizes
– 3-entry instruction TLB
– 3-entry data TLB
– Max issue rate of one 32x16 multiply per clock
– Max issue rate of one 32x32 multiply every other clock
– CPU control with start, stop, and single stepping
– Software breakpoints support
– Hardware breakpoints on virtual addresses
– ICE Interface that is compatible with v2.5 of the EJTAG Spec-
ification
x
PCI Interface
– 32-bit PCI revision 2.2 compliant
– Supports host or satellite operation in both master and target
modes
– Support for synchronous and asynchronous operation
– PCI clock supports frequencies from 16 MHz to 66 MHz
– PCI arbiter in Host mode: supports 6 external masters, fixed
priority or round robin arbitration
–I2O “l(fā)ike” PCI Messaging Unit
x
Ethernet Interface
– 10 and 100 Mb/s ISO/IEC 8802-3:1996 compliant
– Supports MII or RMII PHY interface
– Supports 64 entry hash table based multicast address filtering
– 512 byte transmit and receive FIFOs
– Supports flow control functions outlined in IEEE Std. 802.3x-
1997
x
DDR Memory Controller
– Supports up to 256MB of DDR SDRAM
– 1 chip select supporting 4 internal DDR banks
– Supports a 16-bit wide data port using x8 or x16 bit wide DDR
SDRAM devices
– Supports 64 Mb, 128 Mb, 256 Mb, 512 Mb, and 1Gb DDR
SDRAM devices
– Data bus multiplexing support allows interfacing to standard
DDR DIMMs and SODIMMs
– Automatic refresh generation
B
Block Diagram
lock Diagram
EJTAG
MMU
D. Cache
I. Cache
MIPS-32
CPU Core
ICE
Interrupt
Controller
3 Counter
Timers
DMA
Controller
Arbiter
DDR
1 UART
(16550)
GPIO
Interface
PCI
Master/Target
Memory &
Peripheral Bus (8-bit)
Serial Channel GPIO Pins
PCI Bus
Controller
SPI
SPI Bus
:
10/100
1 Ethernet
Interface
MII/RMII
IPBusTM
Interface
PCI Arbiter
(Host Mode)
PMBus
DDR
Controllers
(16-bit)
Memory & I/O
Controller
Bus/System
Integrity
Monitor
NVRAM
Controller
I2C
Controller
I2C Bus
79RC32435
IDTTM InterpriseTM Integrated
Communications Processor
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