- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄65590 > IDT74LVC161ADC8 (INTEGRATED DEVICE TECHNOLOGY INC) LVC/LCX/Z SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16 PDF資料下載
參數(shù)資料
| 型號(hào)： | IDT74LVC161ADC8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 計(jì)數(shù)器 |
| 英文描述： | LVC/LCX/Z SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁(yè)數(shù)： | 1/7頁(yè) |
| 文件大?。?/td> | 194K |
| 代理商： | IDT74LVC161ADC8 |
INDUSTRIALTEMPERATURERANGE
IDT74LVC161A
3.3VCMOSPRESETTABLE SYNCHRONOUS 4-BIT BINARY COUNTER
1
OCTOBER 1999
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
1999 Integrated Device Technology, Inc.
DSC-5156/3
FEATURES:
0.5 MICRON CMOS Technology
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
CMOS power levels (0.4
μμμμμ W typ. static)
Rail-to-Rail output swing for increased noise margin
All inputs, outputs, and I/Os are 5V tolerant
Supports hot insertion
Available in SOIC and TSSOP packages
FUNCTIONAL DIAGRAM
DRIVE FEATURES:
High Output Drivers: ±24mA
Reduced system switching noise
APPLICATIONS:
5V and 3.3V mixed voltage systems
Data communication and telecommunication systems
IDT74LVC161A
DESCRIPTION:
The LVC161A is a high-performance, low-power, low-voltage, Si-gate
CMOS device, superior to most advanced CMOS-compatible TTL families.
The LVC161A is a presettable synchronous binary counter which
3.3V CMOS PRESETTABLE
SYNCHRONOUS 4-BIT BINARY
COUNTER WITH ASYNCHRONOUS
RESET, 5 VOLT TOLERANT I/O
STATE DIAGRAM
Inputs can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V supply system.
f
max =
tp
(max) (CP to TC) + tsu (CEP to CP)
1
01
2
3
4
5
6
7
8
9
10
11
12
13
14
15
PARALLEL LOAD
CIRCUITRY
BINARY COUNTER
34
5
6
14
13
12
11
Q0
Q1
Q2
Q3
D0
D1
D2
D3
PE
CET
CEP
CP
MR
TC
9
10
7
2
1
15
features an internal look-ahead carry and can be used for high-speed
counting. Synchronous operation is provided by having all flip-flops clocked
simultaniously on the positive-going edge of the clock (CP). Outputs (Q
0 to
Q
3) of the counters may be preset to a high or low level. A low level at the
parallel enable input (
PE) disables the counting action and causes the data
at inputs (D
0 to D3) to be loaded into the counter on the positive-going edge
of the clock (provided that the set-up and hold time requirements for
PE are
met). Preset takes place regardless of the levels at the count enable inputs
(CEP and CET). A low level at the master reset input (
MR)setsallfouroutputs
of the flip-flops (Q
0 to Q3) to low level regardless of the levels at CP, PE, CET,
and CEP inputs (thus providing an asynchronous clear function).
The look-ahead carry simplifies serial cascading of the counters. Both
count enable inputs (CEP and CET) must be high to count. The CET input
is fed forward to enable the terminal count output (TC). The TC output thus
enabled will produce a high output pulse of a duration approximately equal
to a high level output of Q
0. This pulse can be used to enable the next
cascaded stage. The maximum clock frequency for the cascaded counters
is determined by the CP to TC propagation delay and CEP to CP set-up time,
according to the following formula:
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT74LVC162245APFG | LVC/LCX/Z SERIES, DUAL 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48 |
| IDT74LVC16241APV | LVC/LCX/Z SERIES, QUAD 4-BIT DRIVER, TRUE OUTPUT, PDSO48 |
| IDT74LVC16241APV8 | LVC/LCX/Z SERIES, QUAD 4-BIT DRIVER, TRUE OUTPUT, PDSO48 |
| IDT74LVC16241APF | LVC/LCX/Z SERIES, QUAD 4-BIT DRIVER, TRUE OUTPUT, PDSO48 |
| IDT74LVC16241APF8 | LVC/LCX/Z SERIES, QUAD 4-BIT DRIVER, TRUE OUTPUT, PDSO48 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT74LVC162244APA | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT74LVC162244APAG | 功能描述:IC BUFF DVR TRI-ST 16BIT 48TSSOP RoHS:是 類別:集成電路 (IC) >> 邏輯 - 緩沖器，驅(qū)動(dòng)器，接收器，收發(fā)器 系列:74LVC 標(biāo)準(zhǔn)包裝:2,000 系列:74LVCH 邏輯類型:緩沖器/線路驅(qū)動(dòng)器，非反相 元件數(shù):2 每個(gè)元件的位元數(shù):4 輸出電流高，低:24mA，24mA 電源電壓:1.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:20-SOIC 包裝:帶卷 (TR) |
| IDT74LVC162244APAG8 | 功能描述:IC BUFF DVR TRI-ST 16BIT 48TSSOP RoHS:是 類別:集成電路 (IC) >> 邏輯 - 緩沖器，驅(qū)動(dòng)器，接收器，收發(fā)器 系列:74LVC 標(biāo)準(zhǔn)包裝:47 系列:74LVX 邏輯類型:緩沖器/線路驅(qū)動(dòng)器，非反相 元件數(shù):4 每個(gè)元件的位元數(shù):1 輸出電流高，低:4mA，4mA 電源電壓:2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:14-SOIC 包裝:管件 |
| IDT74LVC162244APFG | 功能描述:IC BUFF DVR TRI-ST 16BIT 48TVSOP RoHS:是 類別:集成電路 (IC) >> 邏輯 - 緩沖器，驅(qū)動(dòng)器，接收器，收發(fā)器 系列:74LVC 標(biāo)準(zhǔn)包裝:47 系列:74LVX 邏輯類型:緩沖器/線路驅(qū)動(dòng)器，非反相 元件數(shù):4 每個(gè)元件的位元數(shù):1 輸出電流高，低:4mA，4mA 電源電壓:2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:14-SOIC 包裝:管件 |
| IDT74LVC162244APFG8 | 功能描述:IC BUFF DVR TRI-ST 16BIT 48TVSOP RoHS:是 類別:集成電路 (IC) >> 邏輯 - 緩沖器，驅(qū)動(dòng)器，接收器，收發(fā)器 系列:74LVC 標(biāo)準(zhǔn)包裝:47 系列:74LVX 邏輯類型:緩沖器/線路驅(qū)動(dòng)器，非反相 元件數(shù):4 每個(gè)元件的位元數(shù):1 輸出電流高，低:4mA，4mA 電源電壓:2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:14-SOIC 包裝:管件 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。