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參數(shù)資料
| 型號： | IDT74FCT16652CTPAG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | FCT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | TSSOP-56 |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 102K |
| 代理商： | IDT74FCT16652CTPAG |
3
IDT74FCT16652AT/CT
FASTCMOS16-BITBUSTRANSCEIVER/REGISTER
INDUSTRIALTEMPERATURERANGE
Inputs
Data I/O(1)
xOEAB
xOEBA
xCLKAB
xCLKBA
xSAB
xSBA
xAx
xBx
Operation or Function
L
H
H or L
X
Input
Isolation
LH
↑↑
X
Store A and B Data
XH
↑
H or L
X
Input
Unspecified(1)
Store A, Hold B
HH
↑↑
X(2)
X
Input
Output
Store A in Both Registers
L
X
H or L
↑
X
Unspecified(1)
Input
Hold A, Store B
LL
↑↑
XX(2)
Output
Input
Store B in Both Registers
L
X
L
Output
Input
Real Time B Data to A Bus
L
X
H or L
X
H
Stored B Data to A Bus
H
X
L
X
Input
Output
Real Time A Data to B Bus
H
H or L
X
H
X
Stored A Data to B Bus
H
L
H or L
H
Output
Stored A Data to B Bus and
Stored B Data to A Bus
FUNCTION TABLE
NOTES:
1. The data output functions may be enabled or disabled by various signals at the xOEAB or xOEBA inputs. Data input functions are always enabled, i.e. data at the bus pins
will be stored on every LOW-to-HIGH transition on the clocks inputs.
2. Select control = L: clocks can occur simultaneously.
Select control = H: clocks must be staggered to load both registers.
3. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't care
↑ = LOW-to-HIGH Transition
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| IDT74FCT16652ETPVT/R | FCT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56 |
| IDT74FCT16823BTPV8 | FCT SERIES, DUAL 9-BIT DRIVER, TRUE OUTPUT, PDSO56 |
| IDT74FCT16823ETPF8 | FCT SERIES, DUAL 9-BIT DRIVER, TRUE OUTPUT, PDSO56 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT74FCT16652TPA | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT74FCT16652TPV | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT74FCT16823ATPV | 制造商:INT_DEV_TECH 功能描述: |
| IDT74FCT16823CTPV | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT74FCT16823ETPA | 制造商:Integrated Device Technology Inc 功能描述: |
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