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參數(shù)資料
| 型號： | IDT72V71650BB |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 6/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL SW 8192X8192 144-BGA |
| 標準包裝： | 10 |
| 系列： | 72V |
| 類型： | 多路復用器 |
| 電路： | 1 x 32:32 |
| 獨立電路： | 1 |
| 電壓電源： | 單電源 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-BGA |
| 供應商設備封裝： | 144-PBGA（13x13） |
| 包裝： | 托盤 |
| 其它名稱： | 72V71650BB |
14
INDUSTRIAL TEMPERATURERANGE
IDT72V71650 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 8,192 x 8,192
TABLE 10 — IDENTIFICATION REGISTER DEFINITIONS
INSTRUCTION FIELD
VALUE
DESCRIPTION
Revision Number (31:28)
0x0
Reserved for version number
IDT Device ID (27:12)
0x435
Defines IDT part number
IDT JEDEC ID (11:1)
0x33
Allows unique identification of device vendor as IDT
ID Register Indicator Bit (Bit 0)
1
Indicates the presence of an ID register
REGISTER NAME
BIT SIZE
Instruction (IR)
4
Bypass (BYR)
1
Identification(IDR)
32
Boundary Scan (BSR)
Note(1)
TABLE 11 — SCAN REGISTER SIZES
NOTES:
1. The Boundary Scan Descriptive Language (BSDL) file for this device is available on
the IDT website (www.idt.com), or by contacting your local IDT sales representative.
JTAG SUPPORT
TheIDT72V71650JTAGinterfaceconformstotheBoundary-Scanstandard
IEEE-1149.1.Thisstandardspecifiesadesign-for-testabilitytechniquecalled
Boundary-Scan test (BST). The operation of the boundary-scan circuitry is
controlled by an external test access port (TAP) Controller.
TEST ACCESS PORT (TAP)
The Test Access Port (TAP) provides access to the test functions of the
IDT72V71650. It consists of three input pins and one output pin.
Test Clock Input (TCK)
TCK provides the clock for the test logic. The TCK does not interfere with
any on-chip clock and thus remains independent. The TCK permits shifting of
test data into or out of the Boundary-Scan register cells concurrently with the
operation of the device and without interfering with the on-chip logic.
Test Mode Select Input (TMS)
The logic signals received at the TMS input are interpreted by the TAP
Controller to control the test operations. The TMS signals are sampled at the
rising edge of the TCK pulse. This pin is internally pulled to VCC when it is not
driven from an external source.
Test Data Input (TDI)
Serial input data applied to this port is fed either into the instruction register
or into a test data register, depending on the sequence previously applied to
the TMS input. Both registers are described in a subsequent section. The
received input data is sampled at the rising edge of TCK pulses. This pin is
internally pulled to VCC when it is not driven from an external source.
Test Data Output (TDO)
Depending on the sequence previously applied to the TMS input, the
contentsofeithertheinstructionregisterordataregisterareseriallyshiftedout
through the TDO pin on the falling edge of each TCK pulse. When no data
is shifted through the boundary scan cells, the TDO driver is set to a
high-impedancestate.
Test Reset (TRST)
Reset the JTAG scan structure. This pin is internally pulled to VCC when it
is not driven from an external source.
INSTRUCTION REGISTER
InaccordancewiththeIEEE-1149.1standard,theIDT72V71650usespublic
instructions. The IDT72V71650 JTAG interface contains a four-bit instruction
register.InstructionsareseriallyloadedintotheinstructionregisterfromtheTDI
whentheTAPControllerisinitsshift-IRstate.Subsequently,theinstructionsare
decodedtoachievetwobasicfunctions:toselectthetestdataregisterthatmay
operatewhiletheinstructioniscurrent,andtodefinetheserialtestdataregister
path, which is used to shift data between TDI and TDO during data register
scanning. See Table 12 below for Instruction decoding.
TEST DATA REGISTER
AsspecifiedinIEEE-1149.1,theIDT72V71650JTAGInterfacecontainstwo
testdataregisters:
The Boundary-Scan register
The Boundary-Scan register consists of a series of Boundary-Scan cells
arranged to form a scan path around the boundary of the IDT72V71650 core
logic.
The Bypass Register
TheBypassregisterisasinglestageshiftregisterthatprovidesaone-bitpath
from TDI to TDO. The IDT72V71650 boundary scan register bits are shown
in Table 14. Bit 0 is the first bit clocked out. All three-state enable bits are active
HIGH.
ID CODE REGISTER
As specified in IEEE-1149.1, this instruction loads the IDR with the Revision
Number, Device ID, and ID Register Indicator Bit. See Table 10.
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| IDT72V71660BB | 功能描述:IC DGTL SW 16382X16384 208-BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - 信號開關，多路復用器，解碼器 系列:72V 標準包裝:48 系列:74VHC 類型:多路復用器 電路:4 x 2:1 獨立電路:1 輸出電流高，低:8mA，8mA 電壓電源:單電源 電源電壓:2 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:16-SOIC 包裝:管件 |
| IDT72V71660DR | 功能描述:IC DGTL SW 16382X16384 208-PQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - 信號開關，多路復用器，解碼器 系列:72V 標準包裝:48 系列:74VHC 類型:多路復用器 電路:4 x 2:1 獨立電路:1 輸出電流高，低:8mA，8mA 電壓電源:單電源 電源電壓:2 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:16-SOIC 包裝:管件 |
| IDT72V72100L10BB | 功能描述:IC FIFO 131KX36 10NS 256BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72V72100L10BBG | 功能描述:IC FIFO 131KX36 10NS 256BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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