IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC IITM
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� IDT72V3650L6BB8
寤犲晢锛� IDT, Integrated Device Technology Inc
鏂囦欢闋佹暩(sh霉)锛� 22/46闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FIFO SS 2048X36 6NS 144-BGA
妯欐簴鍖呰锛� 1,000
绯诲垪锛� 72V
鍔熻兘锛� 鐣版锛屽悓姝�
瀛樺劜瀹归噺锛� 72K锛�2K x 36锛�
鏁�(sh霉)鎿�(j霉)閫熺巼锛� 166MHz
瑷晱鏅傞枔锛� 4ns
闆绘簮闆诲锛� 3.15 V ~ 3.45 V
宸ヤ綔婧害锛� 0°C ~ 70°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 144-BGA
渚涙噳鍟嗚ō鍌欏皝瑁濓細 144-PBGA锛�13x13锛�
鍖呰锛� 甯跺嵎 (TR)
鍏跺畠鍚嶇ū锛� 72V3650L6BB8
29
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
OCTOBER 22, 2008
Figure
10.
Read
Timing
(First
Word
Fall
Through
Mode)
NOTES:
1.
t
SKEW1
is
the
minimum
time
between
a
rising
RCLK
edge
and
a
rising
WCLK
edge
to
guarantee
that
IR
will
go
LOW
after
one
WCLK
cycle
plus
t
WFF
.If
the
time
between
the
rising
edge
of
RCLK
and
the
rising
edge
of
WCLK
is
less
than
tSKEW1
,then
the
IR
assertion
may
be
delayed
one
extra
WCLK
cycle.
2.
tSKEW2
is
the
minimum
time
between
a
rising
RCLK
edge
and
a
rising
WCLK
edge
to
guarantee
that
PAF
will
go
HIGH
after
one
WCLK
cycle
plus
t
PAFS
.If
the
time
between
the
rising
edge
of
RCLK
and
the
rising
edge
of
WCLK
is
less
than
tSKEW2
,then
the
PAF
deassertion
may
be
delayed
one
extra
WCLK
cycle.
3.
LD
=
HIGH
4.
n=
PAE
Offset,
m
=
PAF
offset
and
D
=
maximum
FIFO
depth.
5
.
D
=
1,025
for
IDT72V3640,
2,049
for
IDT72V3650,
4,097
for
IDT72V3660,
8,193
for
IDT72V3670,
16,385
for
the
IDT72V3680
and
32,
769
for
the
IDT72V3690.
WCLK
12
WEN
D
0
-
D
17
RCLK
tENS
REN
Q
0
-
Q
17
PAF
HF
PAE
IR
OR
W
1
W
1
W
2
W
3
W
m+2
W
[m+3]
tOHZ
tSKEW1
tENH
tDS
tDH
tOE
tA
tPAFS
tWFF
tENS
OE
tSKEW2
W
D
4667
drw15
tPAES
W
[D-n]
W
[D-n-1]
tA
tHF
tREF
W
[D-1]
W
D
tA
W
[D-n+1]
W
[m+4]
W
[D-n+2]
(1)
(2)
tENS
D-1
+
1
]
[
W
2
D-1
+
2
]
[
W
2
1
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