IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC IITM
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� IDT72V3650L6BB8
寤犲晢锛� IDT, Integrated Device Technology Inc
鏂囦欢闋佹暩(sh霉)锛� 2/46闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FIFO SS 2048X36 6NS 144-BGA
妯欐簴鍖呰锛� 1,000
绯诲垪锛� 72V
鍔熻兘锛� 鐣版锛屽悓姝�
瀛樺劜瀹归噺锛� 72K锛�2K x 36锛�
鏁�(sh霉)鎿�(j霉)閫熺巼锛� 166MHz
瑷晱鏅傞枔锛� 4ns
闆绘簮闆诲锛� 3.15 V ~ 3.45 V
宸ヤ綔婧害锛� 0°C ~ 70°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 144-BGA
渚涙噳鍟嗚ō(sh猫)鍌欏皝瑁濓細 144-PBGA锛�13x13锛�
鍖呰锛� 甯跺嵎 (TR)
鍏跺畠鍚嶇ū锛� 72V3650L6BB8
10
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
OCTOBER 22, 2008
AC ELECTRICAL CHARACTERISTICS(1)鈥� ASYNCHRONOUS TIMING
(Commercial: VCC = 3.3V 卤 0.15V, TA = 0
掳C to +70掳C;Industrial: VCC = 3.3V 卤 0.15V, TA = -40掳C to +85掳C; JEDEC JESD8-A compliant)
Commercial
Com鈥檒 & Ind鈥檒
IDT72V3640L6
IDT72V3640L7-5
IDT72V3650L6
IDT72V3650L7-5
IDT72V3660L6
IDT72V3660L7-5
IDT72V3670L6
IDT72V3670L7-5
IDT72V3680L6
IDT72V3680L7-5
IDT72V3690L6
IDT72V3690L7-5
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
fA(4)
Cycle Frequency (Asynchronous mode)
鈥�
100
鈥�
83
MHz
tAA(4)
Data Access Time
0.6
8
0.6
10
ns
tCYC(4)
Cycle Time
10
鈥�
12
鈥�
ns
tCYH(4)
Cycle HIGH Time
4.5
鈥�
5
鈥�
ns
tCYL(4)
Cycle LOW Time
4.5
鈥�
5
鈥�
ns
tRPE(4)
Read Pulse after
EF HIGH
8
鈥�
10
鈥�
ns
tFFA(4)
Clock to Asynchronous
FF
鈥�8
鈥�
10
ns
tEFA(4)
Clock to Asynchronous
EF
鈥�8
鈥�
10
ns
tPAFA(4)
Clock to Asynchronous Programmable Almost-Full Flag
鈥�
8
鈥�
10
ns
tPAEA(4)
Clock to Asynchronous Programmable Almost-Empty Flag
鈥�
8
鈥�
10
ns
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
4. Paramaeters apply to the PBGA package only.
鐩搁棞(gu膩n)PDF璩囨枡
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鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
IDT72V3650L6PF 鍔熻兘鎻忚堪:IC FIFO SS 2048X36 6NS 128-TQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 閭忚集 - FIFO 绯诲垪:72V 妯欐簴鍖呰:90 绯诲垪:7200 鍔熻兘:鍚屾 瀛樺劜瀹归噺:288K锛�16K x 18锛� 鏁�(sh霉)鎿�(j霉)閫熺巼:100MHz 瑷晱鏅傞枔:10ns 闆绘簮闆诲:4.5 V ~ 5.5 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:64-LQFP 渚涙噳鍟嗚ō(sh猫)鍌欏皝瑁�:64-TQFP锛�14x14锛� 鍖呰:鎵樼洡 鍏跺畠鍚嶇ū:72271LA10PF
IDT72V3650L6PF8 鍔熻兘鎻忚堪:IC FIFO SS 2048X36 6NS 128-TQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 閭忚集 - FIFO 绯诲垪:72V 妯欐簴鍖呰:90 绯诲垪:7200 鍔熻兘:鍚屾 瀛樺劜瀹归噺:288K锛�16K x 18锛� 鏁�(sh霉)鎿�(j霉)閫熺巼:100MHz 瑷晱鏅傞枔:10ns 闆绘簮闆诲:4.5 V ~ 5.5 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:64-LQFP 渚涙噳鍟嗚ō(sh猫)鍌欏皝瑁�:64-TQFP锛�14x14锛� 鍖呰:鎵樼洡 鍏跺畠鍚嶇ū:72271LA10PF
IDT72V3650L6PFG 鍔熻兘鎻忚堪:IC FIFO SS 2048X36 6NS 128-TQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 閭忚集 - FIFO 绯诲垪:72V 妯欐簴鍖呰:90 绯诲垪:7200 鍔熻兘:鍚屾 瀛樺劜瀹归噺:288K锛�16K x 18锛� 鏁�(sh霉)鎿�(j霉)閫熺巼:100MHz 瑷晱鏅傞枔:10ns 闆绘簮闆诲:4.5 V ~ 5.5 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:64-LQFP 渚涙噳鍟嗚ō(sh猫)鍌欏皝瑁�:64-TQFP锛�14x14锛� 鍖呰:鎵樼洡 鍏跺畠鍚嶇ū:72271LA10PF
IDT72V3650L6PFG8 鍔熻兘鎻忚堪:IC FIFO SS 2048X36 6NS 128-TQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 閭忚集 - FIFO 绯诲垪:72V 妯欐簴鍖呰:90 绯诲垪:7200 鍔熻兘:鍚屾 瀛樺劜瀹归噺:288K锛�16K x 18锛� 鏁�(sh霉)鎿�(j霉)閫熺巼:100MHz 瑷晱鏅傞枔:10ns 闆绘簮闆诲:4.5 V ~ 5.5 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:64-LQFP 渚涙噳鍟嗚ō(sh猫)鍌欏皝瑁�:64-TQFP锛�14x14锛� 鍖呰:鎵樼洡 鍏跺畠鍚嶇ū:72271LA10PF
IDT72V3650L7-5BB 鍔熻兘鎻忚堪:IC FIFO SS 2048X36 7-5NS 144BGA RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 閭忚集 - FIFO 绯诲垪:72V 妯欐簴鍖呰:90 绯诲垪:7200 鍔熻兘:鍚屾 瀛樺劜瀹归噺:288K锛�16K x 18锛� 鏁�(sh霉)鎿�(j霉)閫熺巼:100MHz 瑷晱鏅傞枔:10ns 闆绘簮闆诲:4.5 V ~ 5.5 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:64-LQFP 渚涙噳鍟嗚ō(sh猫)鍌欏皝瑁�:64-TQFP锛�14x14锛� 鍖呰:鎵樼洡 鍏跺畠鍚嶇ū:72271LA10PF