IDT72V3612 3.3V, CMOS SyncBiFIFOTM 64 x 36 x 2 COMMERCIALTEMPERATURERANGE DC ELECTRICAL CHARACTERISTI" />
參數(shù)資料
型號(hào): IDT72V3612L15PF
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 22/24頁(yè)
文件大?。?/td> 0K
描述: IC FIFO 64X36X2 15NS 120QFP
標(biāo)準(zhǔn)包裝: 45
系列: 72V
功能: 異步
存儲(chǔ)容量: 4.6K(64 x 36 x2)
數(shù)據(jù)速率: 67MHz
訪問(wèn)時(shí)間: 15ns
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 120-LQFP
供應(yīng)商設(shè)備封裝: 120-TQFP(14x14)
包裝: 托盤(pán)
其它名稱: 72V3612L15PF
7
IDT72V3612 3.3V, CMOS SyncBiFIFOTM
64 x 36 x 2
COMMERCIALTEMPERATURERANGE
DC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF
SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
IDT72V3612L12
IDT72V3612L15
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
fS
Clock Frequency, CLKA or CLKB
83
66.7
MHz
tCLK
Clock Cycle Time, CLKA or CLKB
12
15
ns
tCLKH
Pulse Duration, CLKA and CLKB HIGH
5–6–
ns
tCLKL
Pulse Duration, CLKA and CLKB LOW
5–6–
ns
tDS
Setup Time, A0-A35 before CLKA
↑ and B0-B35 before CLKB↑
4–4–
ns
tENS1
Setup Time, CSA, W/RA before CLKA
↑; CSB, W/RB before CLKB↑
3.5
6
ns
tENS2
Setup Time, ENA, before CLKA
↑; ENB before CLKB↑
3.5
4
ns
tENS3
Setup Time, MBA before CLKA
↑: MBB before CLKB↑
3.5
4
ns
tPGS
Setup Time, ODD/EVEN and PGA before CLKA
↑;
3–4–
ns
ODD/EVEN and PGB before CLKB
(1)
tRSTS
Setup Time, RST LOW before CLKA
↑ or CLKB↑(2)
4–5–
ns
tFSS
Setup Time, FS0/FS1 before RST HIGH
4–5–
ns
tDH
Hold Time, A0-A35 after CLKA
↑ and B0-B35 after CLKB↑
0.5
1
ns
tENH1
Hold Time, CSA W/RA after CLKA
↑; CSB, W/RB after CLKB↑
0.5
1
ns
tENH2
Hold Time, ENA, after CLKA
↑; ENB after CLKB↑
1–1–
ns
tENH3
Hold Time, MBA after CLKA
↑; MBB after CLKB↑
1–1–
ns
tPGH
Hold Time, ODD/EVEN and PGA after CLKA
↑;
0–1–
ns
ODD/EVEN and PGB after CLKB
(1)
tRSTH
Hold Time, RST LOW after CLKA
↑ or CLKB↑(2)
4–5–
ns
tFSH
Hold Time, FS0 and FS1 after RST HIGH
4–4–
ns
tSKEW1(3)
Skew Time, between CLKA
↑ and CLKB↑ for EFA, EFB,
5.5
8
ns
FFA, and FFB
tSKEW2(3,4)
Skew Time, between CLKA
↑ and CLKB↑ for AEA, AEB,14
14
ns
AFA, and AFB
NOTES:
1. Only applies for a clock edge that does a FIFO read.
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
4. Design simulated, not tested.
Commercial: Vcc=3.3V± 0.30V; for 12ns (83MHz) operation, Vcc=3.3V ±0.15V; TA = 0
° C to +70°C; JEDEC JESD8-A compliant
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IDT72V3612L15PQF 功能描述:IC FIFO 64X36X2 15NS 132QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K(16K x 18) 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP(14x14) 包裝:托盤(pán) 其它名稱:72271LA10PF
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