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| 型號(hào)： | IDT72V3611L15PF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 3/19頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO SYNC 64X36 15NS 120-TQFP |
| 標(biāo)準(zhǔn)包裝： | 45 |
| 系列： | 72V |
| 功能： | 同步 |
| 存儲(chǔ)容量： | 2.3K（64 x 36） |
| 數(shù)據(jù)速率： | 67MHz |
| 訪(fǎng)問(wèn)時(shí)間： | 15ns |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 120-LQFP |
| 供應(yīng)商設(shè)備封裝： | 120-TQFP（14x14） |
| 包裝： | 托盤(pán) |
| 其它名稱(chēng)： | 72V3611L15PF |
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IDT72V3611 3.3V, CMOS SyncFIFOTM
64 x 36
COMMERCIALTEMPERATURERANGE
is LOW and from the mail1 register when MBB is HIGH. Mail2 data is always
presentontheport-Adata(A0-A35)outputswhentheyareactive. TheMail1
RegisterFlag(MBF1)issetHIGHbyaLOW-to-HIGHtransitiononCLKBwhen
aport-BreadisselectedbyCSB,W/RB,andENBwithMBBHIGH. TheMail2
RegisterFlag(MBF2)issetHIGHbyaLOW-to-HIGHtransitiononCLKAwhen
aport-AreadisselectedbyCSA,W/RA,andENAwithMBAHIGH. Thedata
inamailregisterremainsintactafteritisreadandchangesonlywhennewdata
iswrittentotheregister. Forrelevantmailregisterandmailregisterflagtiming
diagrams, see Figure 9 and Figure 10.
PARITY CHECKING
The port-A (A0-A35) inputs and port-B (B0-B35) inputs each have four
paritytreestochecktheparityofincoming(oroutgoing)data. Aparityfailure
on one or more bytes of the input bus is reported by a LOW level on the port
ParityErrorFlag(PEFA,PEFB). Oddorevenparitycheckingcanbeselected,
and the Parity Error Flags can be ignored if this feature is not desired.
ParitystatusischeckedoneachinputbusaccordingtotheleveloftheOdd/
Even parity (ODD/EVEN) select input. A parity error on one or more bytes
ofaportisreportedbyaLOWlevelonthecorrespondingportParityErrorFlag
(PEFA, PEFB) output. Port-A bytes are arranged as A0-A8, A9-A17, A18-
A26, and A27-A35, and port-B bytes are arranged as B0-B8, B9-B17, B18-
B26,andB27-B35. WhenOdd/Evenparityisselected,aportParityErrorFlag
(PEFA,PEFB)isLOWifanybyteontheporthasanodd/evennumberofLOW
levelsappliedtoitsbits.
The four parity trees used to check the A0-A35 inputs are shared by the
mail2 register when parity generation is selected for port-A reads
(PGA=HIGH). Whenport-Areadfromthemail2registerwithparitygeneration
is selected with CSA LOW, ENA HIGH, W/RA LOW, MBA HIGH, and PGA
HIGH,theport-AParityErrorFlag(PEFA)isheldHIGHregardlessofthelevels
appliedtotheA0-A35inputs. Likewise,theparitytreesusedtochecktheB0-
B35inputsaresharedbythemail1registerwhenparitygenerationisselected
forport-Breads(PGB=HIGH). Whenaport-Breadfromthemail1registerwith
parity generation is selected with CSB LOW, ENB HIGH, W/RB LOW, MBB
HIGH, and PGB HIGH, the port-B Parity Error Flag (PEFB) is held HIGH
regardless of the levels applied to the B0-B35 inputs.
PARITYGENERATION
A HIGH level on the port-A Parity Generate select (PGA) or port-B Parity
Generate select (PGB) enables the IDT72V3611 to generate parity bits for
portreadsfromaFIFOormailboxregister. Port-AbytesarearrangedasA0-
A8,A9-A17,A18-A26,andA27-A35,withthemostsignificantbitofeachbyte
usedastheparitybit. Port-BbytesarearrangedasB0-B8,B9-B17,B18-B26,
andB27-B35,withthemostsignificantbitofeachbyteusedastheparitybit. A
write to a FIFO or mail register stores the levels applied to all thirty-six inputs
regardlessofthestateoftheParityGenerateselect(PGA,PGB)inputs. When
dataisreadfromaportwithparitygenerationselected,thelowereightbitsof
eachbyteareusedtogenerateaparitybitaccordingtothelevelontheODD/
EVENselect. Thegeneratedparitybitsaresubstitutedforthelevelsoriginally
written to the most significant bits of each byte as the word is read to the data
outputs.
ParitybitsforFIFOdataaregeneratedafterthedataisreadfromtheFIFO
RAMandbeforethedataiswrittentotheoutputregister. Therefore,theport-
B Parity Generate select (PGB) and ODD/EVEN have setup and hold time
constraints to the port-B clock (CLKB) for a rising edge of CLKB used to read
a new word to the FIFO output register.
Thecircuitusedtogenerateparityforthemail1dataissharedbytheport-
B bus (B0-B35) to check parity and the circuit used to generate parity for the
mail2 data is shared by the port-A bus (A0-A35) to check parity. The shared
paritytreesofaportareusedtogenerateparitybitsforthedatainamailregister
whentheportWrite/Readselect(W/RA,W/RB)inputisLOW,theportMailselect
(MBA, MBB) input is HIGH, Chip Select (CSA, CSB) is LOW, Enable (ENA,
ENB) is HIGH, and the port Parity Generate select (PGA, PGB) is HIGH.
Generating parity for mail register data does not change the contents of the
register (see Figure 13 and Figure 14).
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| IDT72V3611L15PF8 | 功能描述:IC FIFO SYNC 64X36 15NS 120-TQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪(fǎng)問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤(pán) 其它名稱(chēng):72271LA10PF |
| IDT72V3611L15PFG | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 64X36 15NS 120TQFP |
| IDT72V3611L15PFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 64X36 15NS 120TQFP |
| IDT72V3611L15PQF | 功能描述:IC FIFO SYNC 64X36 15NS 132-PQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪(fǎng)問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤(pán) 其它名稱(chēng):72271LA10PF |
| IDT72V3611L20PF | 功能描述:IC FIFO SYNC 64X36 20NS 120-TQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪(fǎng)問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤(pán) 其它名稱(chēng):72271LA10PF |
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